vptestmb
Packed Test Mask Byte
VPTESTMB k1 {k2}, zmm2, zmm3/m512
Tests byte integers and sets k-register mask.
Details
Tests packed 8-bit integers by performing a bitwise AND of zmm2 and zmm3/m512, setting each bit in opmask k1 if the result is nonzero (optionally merged with k2). Operates on 64 byte elements in 512-bit vectors and does not modify EFLAGS; this is a destructive AND-test operation that sets mask bits based on non-zero results. Available in 64-bit mode with AVX-512BW extension.
Pseudocode Operation
for i in 0..63:
elem1 ← zmm2[8*i : 8*i+7]
elem2 ← zmm3/m512[8*i : 8*i+7]
k1[i] ← (mask_merge) ? k2[i] : 0
if (elem1 & elem2) != 0 then k1[i] ← 1Example
VPTESTMB k1, zmm2, zmm3/m512
Encoding
Binary Layout
EVEX
+0
opcode
+4
ModRM
+5
Operands
-
dest
AVX-512 opmask register (k0-k7) -
src1
512-bit ZMM AVX-512 register -
src2
512-bit ZMM AVX-512 register or Memory operand
Reference (Intel® SDM)
Instruction Forms
| Opcode | Instruction | Op/En | 64/32-bit Mode | CPUID | Description |
|---|---|---|---|---|---|
| EVEX.128.66.0F38.W0 26 /r | VPTESTMB k2 {k1}, xmm2, xmm3/m128 | A | V/V | (AVX512VL AND AVX512BW) OR AVX10.1 | Bitwise AND of packed byte integers in xmm2 and xmm3/m128 and set mask k2 to reflect the zero/nonzero status of each element of the result, under writemask k1. |
| EVEX.256.66.0F38.W0 26 /r | VPTESTMB k2 {k1}, ymm2, ymm3/m256 | A | V/V | (AVX512VL AND AVX512BW) OR AVX10.1 | Bitwise AND of packed byte integers in ymm2 and ymm3/m256 and set mask k2 to reflect the zero/nonzero status of each element of the result, under writemask k1. |
| EVEX.512.66.0F38.W0 26 /r | VPTESTMB k2 {k1}, zmm2, zmm3/m512 | A | V/V | AVX512BW OR AVX10.1 | Bitwise AND of packed byte integers in zmm2 and zmm3/m512 and set mask k2 to reflect the zero/nonzero status of each element of the result, under writemask k1. |
| EVEX.128.66.0F38.W1 26 /r | VPTESTMW k2 {k1}, xmm2, xmm3/m128 | A | V/V | (AVX512VL AND AVX512BW) OR AVX10.1 | Bitwise AND of packed word integers in xmm2 and xmm3/m128 and set mask k2 to reflect the zero/nonzero status of each element of the result, under writemask k1. |
| EVEX.256.66.0F38.W1 26 /r | VPTESTMW k2 {k1}, ymm2, ymm3/m256 | A | V/V | (AVX512VL AND AVX512BW) OR AVX10.1 | Bitwise AND of packed word integers in ymm2 and ymm3/m256 and set mask k2 to reflect the zero/nonzero status of each element of the result, under writemask k1. |
| EVEX.512.66.0F38.W1 26 /r | VPTESTMW k2 {k1}, zmm2, zmm3/m512 | A | V/V | AVX512BW OR AVX10.1 | Bitwise AND of packed word integers in zmm2 and zmm3/m512 and set mask k2 to reflect the zero/nonzero status of each element of the result, under writemask k1. |
| EVEX.128.66.0F38.W0 27 /r | VPTESTMD k2 {k1}, xmm2, xmm3/m128/m32bcst | B | V/V | (AVX512VL AND AVX512F) OR AVX10.1 | Bitwise AND of packed doubleword integers in xmm2 and xmm3/m128/m32bcst and set mask k2 to reflect the zero/non-zero status of each element of the result, under writemask k1. |
| EVEX.256.66.0F38.W0 27 /r | VPTESTMD k2 {k1}, ymm2, ymm3/m256/m32bcst | B | V/V | (AVX512VL AND AVX512F) OR AVX10.1 | Bitwise AND of packed doubleword integers in ymm2 and ymm3/m256/m32bcst and set mask k2 to reflect the zero/non-zero status of each element of the result, under writemask k1. |
| EVEX.512.66.0F38.W0 27 /r | VPTESTMD k2 {k1}, zmm2, zmm3/m512/m32bcst | B | V/V | AVX512F OR AVX10.1 | Bitwise AND of packed doubleword integers in zmm2 and zmm3/m512/m32bcst and set mask k2 to reflect the zero/non-zero status of each element of the result, under writemask k1. |
| EVEX.128.66.0F38.W1 27 /r | VPTESTMQ k2 {k1}, xmm2, xmm3/m128/m64bcst | B | V/V | (AVX512VL AND AVX512F) OR AVX10.1 | Bitwise AND of packed quadword integers in xmm2 and xmm3/m128/m64bcst and set mask k2 to reflect the zero/non-zero status of each element of the result, under writemask k1. |
| EVEX.256.66.0F38.W1 27 /r | VPTESTMQ k2 {k1}, ymm2, ymm3/m256/m64bcst | B | V/V | (AVX512VL AND AVX512F) OR AVX10.1 | Bitwise AND of packed quadword integers in ymm2 and ymm3/m256/m64bcst and set mask k2 to reflect the zero/non-zero status of each element of the result, under writemask k1. |
| EVEX.512.66.0F38.W1 27 /r | VPTESTMQ k2 {k1}, zmm2, zmm3/m512/m64bcst | B | V/V | AVX512F OR AVX10.1 | Bitwise AND of packed quadword integers in zmm2 and zmm3/m512/m64bcst and set mask k2 to reflect the zero/non-zero status of each element of the result, under writemask k1. VPTESTMB/VPTESTMW/VPTESTMD/VPTESTMQ—Logical AND and Set Mask Vol. 2C 5-654 |
Instruction Operand Encoding
| Op/En | Tuple Type | Operand 1 | Operand 2 | Operand 3 | Operand 4 |
|---|---|---|---|---|---|
| A | Full Mem | ModRM:reg (w) | EVEX.vvvv (r) | ModRM:r/m (r) | N/A |
| B | Full | ModRM:reg (w) | EVEX.vvvv (r) | ModRM:r/m (r) | N/A |
Description
Performs a bitwise logical AND operation on the first source operand (the second operand) and second source operand (the third operand) and stores the result in the destination operand (the first operand) under the writemask. Each bit of the result is set to 1 if the bitwise AND of the corresponding elements of the first and second src operands is non-zero; otherwise it is set to 0.
VPTESTMD/VPTESTMQ: The first source operand is a ZMM/YMM/XMM register. The second source operand can be a
ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a
32/64-bit memory location. The destination operand is a mask register updated under the writemask.
VPTESTMB/VPTESTMW: The first source operand is a ZMM/YMM/XMM register. The second source operand can be a
ZMM/YMM/XMM register or a 512/256/128-bit memory location. The destination operand is a mask register updated under the writemask.
Operation
VPTESTMB (EVEX encoded versions) (KL, VL) = (16, 128), (32, 256), (64, 512) FOR j := 0 TO KL-1 i := j * 8 IF k1[j] OR *no writemask* THEN DEST[j] := (SRC1[i+7:i] BITWISE AND SRC2[i+7:i] != 0)? 1 : 0; ELSE DEST[j] = 0 ; zeroing-masking only FI; ENDFOR DEST[MAX_KL-1:KL] := 0 VPTESTMW (EVEX encoded versions) (KL, VL) = (8, 128), (16, 256), (32, 512) FOR j := 0 TO KL-1 i := j * 16 IF k1[j] OR *no writemask* THEN DEST[j] := (SRC1[i+15:i] BITWISE AND SRC2[i+15:i] != 0)? 1 : 0; ELSE DEST[j] = 0 ; zeroing-masking only FI; ENDFOR DEST[MAX_KL-1:KL] := 0 VPTESTMB/VPTESTMW/VPTESTMD/VPTESTMQ—Logical AND and Set Mask Vol. 2C 5-655 VPTESTMD (EVEX encoded versions) (KL, VL) = (4, 128), (8, 256), (16, 512) FOR j := 0 TO KL-1 i := j * 32 IF k1[j] OR *no writemask* THEN IF (EVEX.b = 1) AND (SRC2 *is memory*) THEN DEST[j] := (SRC1[i+31:i] BITWISE AND SRC2[31:0] != 0)? 1 : 0; ELSE DEST[j] := (SRC1[i+31:i] BITWISE AND SRC2[i+31:i] != 0)? 1 : 0; FI; ELSE DEST[j] := 0 ; zeroing-masking only FI; ENDFOR DEST[MAX_KL-1:KL] := 0 VPTESTMQ (EVEX encoded versions) (KL, VL) = (2, 128), (4, 256), (8, 512) FOR j := 0 TO KL-1 i := j * 64 IF k1[j] OR *no writemask* THEN IF (EVEX.b = 1) AND (SRC2 *is memory*) THEN DEST[j] := (SRC1[i+63:i] BITWISE AND SRC2[63:0] != 0)? 1 : 0; ELSE DEST[j] := (SRC1[i+63:i] BITWISE AND SRC2[i+63:i] != 0)? 1 : 0; FI; ELSE DEST[j] := 0 ; zeroing-masking only FI; ENDFOR DEST[MAX_KL-1:KL] := 0
Intel C/C++ Compiler Intrinsic Equivalent
VPTESTMB __mmask64 _mm512_test_epi8_mask( __m512i a, __m512i b); VPTESTMB __mmask64 _mm512_mask_test_epi8_mask(__mmask64, __m512i a, __m512i b); VPTESTMW __mmask32 _mm512_test_epi16_mask( __m512i a, __m512i b); VPTESTMW __mmask32 _mm512_mask_test_epi16_mask(__mmask32, __m512i a, __m512i b); VPTESTMD __mmask16 _mm512_test_epi32_mask( __m512i a, __m512i b); VPTESTMD __mmask16 _mm512_mask_test_epi32_mask(__mmask16, __m512i a, __m512i b); VPTESTMQ __mmask8 _mm512_test_epi64_mask(__m512i a, __m512i b); VPTESTMQ __mmask8 _mm512_mask_test_epi64_mask(__mmask8, __m512i a, __m512i b);
Exceptions
SIMD Floating-Point Exceptions
None.
Other Exceptions
VPTESTMD/Q: See Table 2-51, “Type E4 Class Exception Conditions.”
VPTESTMB/W: See Exceptions Type E4.nb in Table 2-51, “Type E4 Class Exception Conditions.”
VPTESTMB/VPTESTMW/VPTESTMD/VPTESTMQ—Logical AND and Set Mask Vol. 2C 5-656