cvtss2sq

Convert Scalar Single-Precision to Signed Quadword Integer

CVTSS2SQ r64, xmm/m32

Converts float to 64-bit integer (Rounded).

Details

Converts the low 32-bit single-precision floating-point value from the source XMM register or memory to a signed 64-bit integer, using the current rounding mode from MXCSR. The result is stored in the destination 64-bit general-purpose register. This instruction is only available in 64-bit mode and sets no flags.

Pseudocode Operation

dest ← ConvertSinglePrecisionToInt64(src[31:0]);

Example

CVTSS2SQ rax, xmm1

Encoding

Binary Layout

Format SSE

Opcode F3 REX.W 0F 2D /r

Extension Base (64-bit)

Operands

dest
64-bit general-purpose register (e.g. RAX)
src
128-bit XMM register or 32-bit memory

Reference (Intel® SDM)

Instruction Forms

Opcode	Instruction	Op/En	64/32-bit Mode	CPUID	Description
F3 0F 2D /r	CVTSS2SI r32, xmm1/m32	A	V/V	SSE	Convert one single precision floating-point value from xmm1/m32 to one signed doubleword integer in r32.
F3 REX.W 0F 2D /r	CVTSS2SI r64, xmm1/m32	A	V/N.E.	SSE A AVX A AVX	Convert one single precision floating-point value from xmm1/m32 to one signed quadword integer in r64. VEX.LIG.F3.0F.W0 2D /r 1 V/V Convert one single precision floating-point value from VCVTSS2SI r32, xmm1/m32 xmm1/m32 to one signed doubleword integer in r32. VEX.LIG.F3.0F.W1 2D /r 1 V/N.E.2 Convert one single precision floating-point value from VCVTSS2SI r64, xmm1/m32 xmm1/m32 to one signed quadword integer in r64.
EVEX.LLIG.F3.0F.W0 2D /r	VCVTSS2SI r32, xmm1/m32{er}	B	V/V	AVX512F OR AVX10.1	Convert one single precision floating-point value from xmm1/m32 to one signed doubleword integer in r32.
EVEX.LLIG.F3.0F.W1 2D /r	VCVTSS2SI r64, xmm1/m32{er}	B	V/N.E.2	AVX512F OR AVX10.1	Convert one single precision floating-point value from xmm1/m32 to one signed quadword integer in r64.

Instruction Operand Encoding

Op/En	Tuple Type	Operand 1	Operand 2	Operand 3	Operand 4
A	N/A	ModRM:reg (w)	ModRM:r/m (r)	N/A	N/A
B	Tuple1 Fixed	ModRM:reg (w)	ModRM:r/m (r)	N/A	N/A

Description

Converts a single precision floating-point value in the source operand (the second operand) to a signed integer in the destination operand (the first operand). The source operand can be an XMM register or a memory location. The destination operand is a general-purpose register. When the source operand is an XMM register, the single precision floating-point value is contained in the low doubleword of the register. When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR register or the embedded rounding control bits. If a converted result exceeds the range limits of signed doubleword integer (in non-64-bit modes or 64-bit mode with REX.W/VEX.W/EVEX.W=0), the floating-point invalid exception is raised, and if this exception is masked, the indefinite integer value 80000000H is returned. If a converted result exceeds the range limits of signed quadword integer (in 64-bit mode and REX.W/VEX.W/EVEX.W = 1), the floating-point invalid exception is raised, and if this exception is masked, the indefinite integer value 80000000_00000000H is returned. Legacy SSE instructions: In 64-bit mode, Use of the REX.W prefix promotes the instruction to produce 64-bit data. See the summary chart at the beginning of this section for encoding data and limits. VEX.W1 and EVEX.W1 versions: promotes the instruction to produce 64-bit data in 64-bit mode. Note: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b, otherwise instructions will #UD. Software should ensure VCVTSS2SI is encoded with VEX.L=0. Encoding VCVTSS2SI with VEX.L=1 may encounter unpredictable behavior across different processor generations. CVTSS2SI—Convert Scalar Single Precision Floating-Point Value to Signed Integer Vol. 2A 3-242

Operation

VCVTSS2SI (EVEX Encoded Version)
IF (SRC *is register*) AND (EVEX.b = 1)
THEN
SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(EVEX.RC);
ELSE
SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(MXCSR.RC);
FI;
IF 64-bit Mode and OperandSize = 64
THEN
DEST[63:0] := Convert_Single_Precision_Floating_Point_To_Integer(SRC[31:0]);
ELSE
DEST[31:0] := Convert_Single_Precision_Floating_Point_To_Integer(SRC[31:0]);
FI;

(V)CVTSS2SI (Legacy and VEX.128 Encoded Version)
IF 64-bit Mode and OperandSize = 64
THEN
DEST[63:0] := Convert_Single_Precision_Floating_Point_To_Integer(SRC[31:0]);
ELSE
DEST[31:0] := Convert_Single_Precision_Floating_Point_To_Integer(SRC[31:0]);
FI;

Intel C/C++ Compiler Intrinsic Equivalent

VCVTSS2SI int _mm_cvtss_i32( __m128 a);
VCVTSS2SI int _mm_cvt_roundss_i32( __m128 a, int r);
VCVTSS2SI __int64 _mm_cvtss_i64( __m128 a);
VCVTSS2SI __int64 _mm_cvt_roundss_i64( __m128 a, int r);

Exceptions

SIMD Floating-Point Exceptions

Invalid, Precision.

Other Exceptions

VEX-encoded instructions, see Table 2-20, “Type 3 Class Exception Conditions,” additionally: #UD If VEX.vvvv != 1111B. EVEX-encoded instructions, see Table 2-50, “Type E3NF Class Exception Conditions.” CVTSS2SI—Convert Scalar Single Precision Floating-Point Value to Signed Integer Vol. 2A 3-243