aesimc

AES Inverse Mix Columns

AESIMC xmm1, xmm2/m128

Performs AES InvMixColumns transformation (decryption helper).

Details

Performs the AES InvMixColumns transformation on a 128-bit XMM register, applying the inverse MixColumns step used in AES block cipher decryption. This is a cryptographic acceleration instruction from the AES-NI extension that operates on 128-bit values and produces no flag modifications.

Pseudocode Operation

dest ← InvMixColumns(src)

Example

AESIMC xmm1, xmm2/m128

Encoding

Binary Layout
66
+0
0F
+1
38
+2
DB
+3
 
Format AES-NI
Opcode 66 0F 38 DB
Extension AES-NI

Operands

  • dest
    128-bit XMM SIMD register
  • src
    128-bit XMM SIMD register or Memory operand

Reference (Intel® SDM)

Instruction Forms

Opcode Instruction Op/En 64/32-bit Mode CPUID Description
66 0F 38 DB /r AESIMC xmm1, xmm2/m128 RM V/V AES Perform the InvMixColumn transformation on a 128-bit round key from xmm2/m128 and store the result in xmm1.
VEX.128.66.0F38.WIG DB /r VAESIMC xmm1, xmm2/m128 RM V/V Both AES Perform the InvMixColumn transformation on and a 128-bit round key from xmm2/m128 and AVX flags store the result in xmm1.

Description

Perform the InvMixColumns transformation on the source operand and store the result in the destination operand. The destination operand is an XMM register. The source operand can be an XMM register or a 128-bit memory location. Note: the AESIMC instruction should be applied to the expanded AES round keys (except for the first and last round key) in order to prepare them for decryption using the “Equivalent Inverse Cipher” (defined in FIPS 197). 128-bit Legacy SSE version: Bits (MAXVL-1:128) of the corresponding YMM destination register remain unchanged. VEX.128 encoded version: Bits (MAXVL-1:128) of the destination YMM register are zeroed. Note: In VEX-encoded versions, VEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.

Operation

AESIMC
DEST[127:0] := InvMixColumns( SRC );
DEST[MAXVL-1:128] (Unmodified)

VAESIMC
DEST[127:0] := InvMixColumns( SRC );
DEST[MAXVL-1:128] := 0;

Intel C/C++ Compiler Intrinsic Equivalent

(V)AESIMC __m128i _mm_aesimc (__m128i)

Exceptions

SIMD Floating-Point Exceptions

None.

Other Exceptions

See Table 2-21, “Type 4 Class Exception Conditions,” additionally: #UD If VEX.vvvv ≠ 1111B. AESIMC—Perform the AES InvMixColumn Transformation Vol. 2A 3-57