cvtsi2ss
Convert Doubleword Integer to Scalar Single-Precision
CVTSI2SS xmm, r/m32
Converts 32-bit int to float.
Details
Converts a 32-bit signed integer operand to a scalar single-precision floating-point value and stores the result in the low 32-bit lane of the destination XMM register, leaving the upper 96 bits unchanged. No traditional flags are affected. Available in SSE and later; the conversion follows IEEE 754 rounding rules.
Pseudocode Operation
src_int ← [src] (sign-extended if r/m32)
fp_value ← convert_int32_to_float(src_int)
dest.float32[0] ← fp_value
// dest.float32[1..3] unchangedExample
CVTSI2SS xmm0, ebx
Encoding
Binary Layout
F3
+0
0F
+1
2A
+2
Operands
-
dest
128-bit SSE/AVX register (XMM) -
src
32-bit register or memory
Reference (Intel® SDM)
Instruction Forms
| Opcode | Instruction | Op/En | 64/32-bit Mode | CPUID | Description |
|---|---|---|---|---|---|
| F3 0F 2A /r | CVTSI2SS xmm1, r/m32 | A | V/V | SSE | Convert one signed doubleword integer from r/m32 to one single precision floating-point value in xmm1. |
| F3 REX.W 0F 2A /r | CVTSI2SS xmm1, r/m64 | A | V/N.E. | SSE | Convert one signed quadword integer from r/m64 to one single precision floating-point value in xmm1. |
| VEX.LIG.F3.0F.W0 2A /r | VCVTSI2SS xmm1, xmm2, r/m32 | B | V/V | AVX | Convert one signed doubleword integer from r/m32 to one single precision floating-point value in xmm1. |
| VEX.LIG.F3.0F.W1 2A /r | VCVTSI2SS xmm1, xmm2, r/m64 | B | V/N.E.1 | AVX | Convert one signed quadword integer from r/m64 to one single precision floating-point value in xmm1. |
| EVEX.LLIG.F3.0F.W0 2A /r | VCVTSI2SS xmm1, xmm2, r/m32{er} | C | V/V | AVX512F OR AVX10.1 | Convert one signed doubleword integer from r/m32 to one single precision floating-point value in xmm1. |
| EVEX.LLIG.F3.0F.W1 2A /r | VCVTSI2SS xmm1, xmm2, r/m64{er} | C | V/N.E.1 | AVX512F OR AVX10.1 | Convert one signed quadword integer from r/m64 to one single precision floating-point value in xmm1. |
Instruction Operand Encoding
| Op/En | Tuple Type | Operand 1 | Operand 2 | Operand 3 | Operand 4 |
|---|---|---|---|---|---|
| A | N/A | ModRM:reg (w) | ModRM:r/m (r) | N/A | N/A |
| B | N/A | ModRM:reg (w) | VEX.vvvv (r) | ModRM:r/m (r) | N/A |
| C | Tuple1 Scalar | ModRM:reg (w) | EVEX.vvvv (r) | ModRM:r/m (r) | N/A |
Description
Converts a signed doubleword or quadword integer in the “convert-from” source operand to a single precision floating-point value in the destination operand (first operand). The “convert-from” source operand can be a general-purpose register or a memory location. The destination operand is an XMM register. The result is stored in the low doubleword of the destination operand, and the upper three doublewords are left unchanged. When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR register or the embedded rounding control bits.
128-bit Legacy SSE version: In 64-bit mode, Use of the REX.W prefix promotes the instruction to use 64-bit input value. The “convert-from” source operand (the second operand) is a general-purpose register or memory location.
Bits (MAXVL-1:32) of the corresponding destination register remain unchanged.
VEX.128 and EVEX encoded versions: The “convert-from” source operand (the third operand) can be a generalpurpose register or a memory location. The first source and destination operands are XMM registers. Bits (127:32) of the XMM register destination are copied from corresponding bits in the first source operand. Bits (MAXVL-1:128) of the destination register are zeroed.
EVEX encoded version: the converted result in written to the low doubleword element of the destination under the writemask.
Software should ensure VCVTSI2SS is encoded with VEX.L=0. Encoding VCVTSI2SS with VEX.L=1 may encounter unpredictable behavior across different processor generations.
CVTSI2SS—Convert Signed Integer to Scalar Single Precision Floating-Point Value Vol. 2A 3-238
Operation
VCVTSI2SS (EVEX Encoded Version) IF (SRC2 *is register*) AND (EVEX.b = 1) THEN SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(EVEX.RC); ELSE SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(MXCSR.RC); FI; IF 64-Bit Mode And OperandSize = 64 THEN DEST[31:0] := Convert_Integer_To_Single_Precision_Floating_Point(SRC[63:0]); ELSE DEST[31:0] := Convert_Integer_To_Single_Precision_Floating_Point(SRC[31:0]); FI; DEST[127:32] := SRC1[127:32] DEST[MAXVL-1:128] := 0 VCVTSI2SS (VEX.128 Encoded Version) IF 64-Bit Mode And OperandSize = 64 THEN DEST[31:0] := Convert_Integer_To_Single_Precision_Floating_Point(SRC[63:0]); ELSE DEST[31:0] := Convert_Integer_To_Single_Precision_Floating_Point(SRC[31:0]); FI; DEST[127:32] := SRC1[127:32] DEST[MAXVL-1:128] := 0 CVTSI2SS (128-bit Legacy SSE Version) IF 64-Bit Mode And OperandSize = 64 THEN DEST[31:0] := Convert_Integer_To_Single_Precision_Floating_Point(SRC[63:0]); ELSE DEST[31:0] :=Convert_Integer_To_Single_Precision_Floating_Point(SRC[31:0]); FI; DEST[MAXVL-1:32] (Unmodified)
Intel C/C++ Compiler Intrinsic Equivalent
VCVTSI2SS __m128 _mm_cvti32_ss(__m128 s, int a); VCVTSI2SS __m128 _mm_cvt_roundi32_ss(__m128 s, int a, int r); VCVTSI2SS __m128 _mm_cvti64_ss(__m128 s, __int64 a); VCVTSI2SS __m128 _mm_cvt_roundi64_ss(__m128 s, __int64 a, int r); CVTSI2SS __m128 _mm_cvtsi64_ss(__m128 s, __int64 a); CVTSI2SS __m128 _mm_cvtsi32_ss(__m128 a, int b);
Exceptions
SIMD Floating-Point Exceptions
Precision.
Other Exceptions
VEX-encoded instructions, see Table 2-20, “Type 3 Class Exception Conditions.”
EVEX-encoded instructions, see Table 2-50, “Type E3NF Class Exception Conditions.”
CVTSI2SS—Convert Signed Integer to Scalar Single Precision Floating-Point Value Vol. 2A 3-239