kandnw

Bitwise Logical AND NOT Masks Word

KANDNW k1, k2, k3

Bitwise AND NOT of 16-bit masks.

Details

Performs a bitwise AND NOT operation (NOT src1 AND src2) on two 16-bit AVX-512 opmask registers and stores the result in a third opmask register. This is a mask-only operation that does not affect EFLAGS. Bits above 16 in the destination are zeroed.

Pseudocode Operation

k1[15:0] ← (~k2[15:0]) & k3[15:0]; k1[63:16] ← 0;

Example

KANDNW k1, k2, k3

Encoding

Binary Layout
EVEX
+0
0F
+4
42
+5
 
Format EVEX
Opcode VEX.L1.0F.W0 42 /r
Extension AVX-512

Operands

  • dest
    AVX-512 opmask register (k0-k7)
  • src1
    AVX-512 opmask register (k0-k7)
  • src2
    AVX-512 opmask register (k0-k7)

Reference (Intel® SDM)

Instruction Forms

Opcode Instruction Op/En 64/32-bit Mode CPUID Description
VEX.L1.0F.W0 42 /r KANDNW k1, k2, k3 V/V RVR AVX512F OR AVX10.1 Bitwise AND NOT 16 bits masks k2 and k3 and place result in k1.
VEX.L1.66.0F.W0 42 /r KANDNB k1, k2, k3 V/V RVR AVX512DQ OR AVX10.1 Bitwise AND NOT 8 bits masks k1 and k2 and place result in k1.
VEX.L1.0F.W1 42 /r KANDNQ k1, k2, k3 V/V RVR AVX512BW OR AVX10.1 Bitwise AND NOT 64 bits masks k2 and k3 and place result in k1.
VEX.L1.66.0F.W1 42 /r KANDND k1, k2, k3 V/V RVR AVX512BW OR AVX10.1 Bitwise AND NOT 32 bits masks k2 and k3 and place result in k1.

Description

Performs a bitwise AND NOT between the vector mask k2 and the vector mask k3, and writes the result into vector mask k1.

Operation

KANDNW
DEST[15:0] := (BITWISE NOT SRC1[15:0]) BITWISE AND SRC2[15:0]
DEST[MAX_KL-1:16] := 0

KANDNB
DEST[7:0] := (BITWISE NOT SRC1[7:0]) BITWISE AND SRC2[7:0]
DEST[MAX_KL-1:8] := 0

KANDNQ
DEST[63:0] := (BITWISE NOT SRC1[63:0]) BITWISE AND SRC2[63:0]
DEST[MAX_KL-1:64] := 0

KANDND
DEST[31:0] := (BITWISE NOT SRC1[31:0]) BITWISE AND SRC2[31:0]
DEST[MAX_KL-1:32] := 0

Intel C/C++ Compiler Intrinsic Equivalent

KANDNW __mmask16 _mm512_kandn(__mmask16 a, __mmask16 b);

Flags Affected

None.

Exceptions

SIMD Floating-Point Exceptions

None.

Other Exceptions

See Table 2-65, “TYPE K20 Exception Definition (VEX-Encoded OpMask Instructions w/o Memory Arg).” KANDNW/KANDNB/KANDNQ/KANDND—Bitwise Logical AND NOT Masks Vol. 2A 3-515