blcfill

Fill From Lowest Clear Bit

BLCFILL r32, r/m32

Sets all bits below the lowest clear bit (x & (x+1)).

Details

Fills all bits from the lowest clear bit position downward; computes (src & (src+1)) and stores the result in dest. This sets all bits below and including the position of the lowest 0-bit in the source. No flags are modified by this TBM instruction.

Pseudocode Operation

result ← src & (src + 1)
dest ← result

Example

BLCFILL eax, ebx

Encoding

Binary Layout
VEX
+0
opcode
+3
ModRM
+4
 
Format TBM
Opcode XOP.L0.09.W0 01 /1
Extension TBM

Operands

  • dest
    32-bit general-purpose register (e.g. EAX)
  • src
    32-bit register or memory

Reference (AMD APM)

Instruction Forms

Opcode Instruction Op/En 64/32-bit Mode CPUID Description
8F RXB.09 0.dest.0.00 01 /1 BLCFILL reg32, reg/mem32
8F RXB.09 1.dest.0.00 01 /1 BLCFILL reg64, reg/mem64

Description

Finds the least significant zero bit in the source operand, clears all bits below that bit to 0 and writes the result to the destination. If there is no zero bit in the source operand, the destination is written with all zeros. This instruction has two operands: BLCFILL dest, src In 64-bit mode, the operand size is determined by the value of XOP.W. If XOP.W is 1, the operand size is 64-bit; if XOP.W is 0, the operand size is 32-bit. In 32-bit mode, XOP.W is ignored. 16-bit operands are not supported. The destination (dest) is a general purpose register. The source operand (src) is a general purpose register or a memory operand. The BLCFILL instruction effectively performs a bit-wise logical and of the source operand and the result of incrementing the source operand by 1 and stores the result to the destination register: add tmp, src, 1 and dest,tmp, src The value of the carry flag of rFLAGS is generated according to the result of the add pseudoinstruction and the remaining arithmetic flags are generated by the and pseudo-instruction. The BLCFILL instruction is a TBM instruction. Support for this instruction is indicated by CPUID Fn8000_0001_ECX[TBM] = 1. For more information on using the CPUID instruction, see the instruction reference page for the CPUID instruction on page 165. For a description of all feature flags related to instruction subset support, see Appendix D, “Instruction Subsets and CPUID Feature Flags,” on page 593.