vreduceps

Perform Reduction Transformation Packed Single

VREDUCEPS zmm1 {k1}, zmm2/m512, imm8

Performs reduction on floats (e.g. range reduction for trig).

Details

The Perform Reduction Transformation Packed Single instruction performs reduction on floats (e.g. range reduction for trig).

Pseudocode Operation

// Performs reduction on floats (e.g. range reduction for trig)

Example

VREDUCEPS zmm1, zmm2/m512, 3

Encoding

Binary Layout
EVEX
+0
66
+4
0F
+5
3A
+6
56
+7
 
Format EVEX
Opcode 66 0F 3A 56
Extension AVX-512DQ

Operands

  • dest
    512-bit ZMM AVX-512 register
  • src1
    512-bit ZMM AVX-512 register or Memory operand
  • src2
    8-bit signed immediate