subps
Subtract Packed Single-Precision
Subtracts four 32-bit floats.
Pseudocode Operation
dest[31:0] ← dest[31:0] - src[31:0];
dest[63:32] ← dest[63:32] - src[63:32];
dest[95:64] ← dest[95:64] - src[95:64];
dest[127:96] ← dest[127:96] - src[127:96];Example
Encoding
Operands
-
dest
128-bit SSE/AVX register (XMM) -
src
128-bit XMM register or 128-bit memory
Related
More in SSE
Reference
Instruction Forms
| Opcode | Instruction | Op/En | 64/32-bit Mode | CPUID | Description |
|---|---|---|---|---|---|
| NP 0F 5C /r | SUBPS xmm1, xmm2/m128 | A | V/V | SSE | Subtract packed single precision floating-point values in xmm2/mem from xmm1 and store result in xmm1. |
| VEX.128.0F.WIG 5C /r | VSUBPS xmm1,xmm2, xmm3/m128 | B | V/V | AVX | Subtract packed single precision floating-point values in xmm3/mem from xmm2 and stores result in xmm1. |
| VEX.256.0F.WIG 5C /r | VSUBPS ymm1, ymm2, ymm3/m256 | B | V/V | AVX | Subtract packed single precision floating-point values in ymm3/mem from ymm2 and stores result in ymm1. |
| EVEX.128.0F.W0 5C /r | VSUBPS xmm1 {k1}{z}, xmm2, xmm3/m128/m32bcst | C | V/V | (AVX512VL AND AVX512F) OR AVX10.1 | Subtract packed single precision floating-point values from xmm3/m128/m32bcst to xmm2 and stores result in xmm1 with writemask k1. |
| EVEX.256.0F.W0 5C /r | VSUBPS ymm1 {k1}{z}, ymm2, ymm3/m256/m32bcst | C | V/V | (AVX512VL AND AVX512F) OR AVX10.1 | Subtract packed single precision floating-point values from ymm3/m256/m32bcst to ymm2 and stores result in ymm1 with writemask k1. |
| EVEX.512.0F.W0 5C /r | VSUBPS zmm1 {k1}{z}, zmm2, zmm3/m512/m32bcst{er} | C | V/V | AVX512F OR AVX10.1 | Subtract packed single precision floating-point values in zmm3/m512/m32bcst from zmm2 and stores result in zmm1 with writemask k1. |
Instruction Operand Encoding
| Op/En | Tuple Type | Operand 1 | Operand 2 | Operand 3 | Operand 4 |
|---|---|---|---|---|---|
| A | N/A | ModRM:reg (r, w) | ModRM:r/m (r) | N/A | N/A |
| B | N/A | ModRM:reg (w) | VEX.vvvv (r) | ModRM:r/m (r) | N/A |
| C | Full | ModRM:reg (w) | EVEX.vvvv (r) | ModRM:r/m (r) | N/A |
Description
Performs a SIMD subtract of the packed single precision floating-point values in the second Source operand from the First Source operand, and stores the packed single precision floating-point results in the destination operand. VEX.128 and EVEX.128 encoded versions: The second source operand is an XMM register or an 128-bit memory location. The first source operand and destination operands are XMM registers. Bits (MAXVL-1:128) of the corresponding destination register are zeroed. VEX.256 and EVEX.256 encoded versions: The second source operand is an YMM register or an 256-bit memory location. The first source operand and destination operands are YMM registers. Bits (MAXVL-1:256) of the corresponding destination register are zeroed. EVEX.512 encoded version: The second source operand is a ZMM register, a 512-bit memory location or a 512-bit vector broadcasted from a 32-bit memory location. The first source operand and destination operands are ZMM registers. The destination operand is conditionally updated according to the writemask. 128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The destination is not distinct from the first source XMM register and the upper Bits (MAXVL-1:128) of the corresponding register destination are unmodified.
Operation
VSUBPS (EVEX Encoded Versions When SRC2 Operand is a Vector Register) (KL, VL) = (4, 128), (8, 256), (16, 512) IF (VL = 512) AND (EVEX.b = 1) THEN SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(EVEX.RC); ELSE SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(MXCSR.RC); FI; FOR j := 0 TO KL-1 i := j * 32 IF k1[j] OR *no writemask* THEN DEST[i+31:i] := SRC1[i+31:i] - SRC2[i+31:i] ELSE IF *merging-masking* ; merging-masking THEN *DEST[31:0] remains unchanged* ELSE ; zeroing-masking DEST[31:0] := 0 FI; FI; ENDFOR; DEST[MAXVL-1:VL] := 0 VSUBPS (EVEX Encoded Versions When SRC2 Operand is a Memory Source) (KL, VL) = (4, 128), (8, 256), (16, 512) FOR j := 0 TO KL-1 i := j * 32 IF k1[j] OR *no writemask* THEN IF (EVEX.b = 1) THEN DEST[i+31:i] := SRC1[i+31:i] - SRC2[31:0]; ELSE DEST[i+31:i] := SRC1[i+31:i] - SRC2[i+31:i]; FI; ELSE IF *merging-masking* ; merging-masking THEN *DEST[31:0] remains unchanged* ELSE ; zeroing-masking DEST[31:0] := 0 FI; FI; ENDFOR; DEST[MAXVL-1:VL] := 0 VSUBPS (VEX.256 Encoded Version) DEST[31:0] := SRC1[31:0] - SRC2[31:0] DEST[63:32] := SRC1[63:32] - SRC2[63:32] DEST[95:64] := SRC1[95:64] - SRC2[95:64] DEST[127:96] := SRC1[127:96] - SRC2[127:96] DEST[159:128] := SRC1[159:128] - SRC2[159:128] DEST[191:160] := SRC1[191:160] - SRC2[191:160] DEST[223:192] := SRC1[223:192] - SRC2[223:192] DEST[255:224] := SRC1[255:224] - SRC2[255:224]. DEST[MAXVL-1:256] := 0 VSUBPS (VEX.128 Encoded Version) DEST[31:0] := SRC1[31:0] - SRC2[31:0] DEST[63:32] := SRC1[63:32] - SRC2[63:32] DEST[95:64] := SRC1[95:64] - SRC2[95:64] DEST[127:96] := SRC1[127:96] - SRC2[127:96] DEST[MAXVL-1:128] := 0 SUBPS (128-bit Legacy SSE Version) DEST[31:0] := SRC1[31:0] - SRC2[31:0] DEST[63:32] := SRC1[63:32] - SRC2[63:32] DEST[95:64] := SRC1[95:64] - SRC2[95:64] DEST[127:96] := SRC1[127:96] - SRC2[127:96] DEST[MAXVL-1:128] (Unmodified)
Intel C/C++ Compiler Intrinsic Equivalent
VSUBPS __m512 _mm512_sub_ps (__m512 a, __m512 b); VSUBPS __m512 _mm512_mask_sub_ps (__m512 s, __mmask16 k, __m512 a, __m512 b); VSUBPS __m512 _mm512_maskz_sub_ps (__mmask16 k, __m512 a, __m512 b); VSUBPS __m512 _mm512_sub_round_ps (__m512 a, __m512 b, int); VSUBPS __m512 _mm512_mask_sub_round_ps (__m512 s, __mmask16 k, __m512 a, __m512 b, int); VSUBPS __m512 _mm512_maskz_sub_round_ps (__mmask16 k, __m512 a, __m512 b, int); VSUBPS __m256 _mm256_sub_ps (__m256 a, __m256 b); VSUBPS __m256 _mm256_mask_sub_ps (__m256 s, __mmask8 k, __m256 a, __m256 b); VSUBPS __m256 _mm256_maskz_sub_ps (__mmask16 k, __m256 a, __m256 b); SUBPS __m128 _mm_sub_ps (__m128 a, __m128 b); VSUBPS __m128 _mm_mask_sub_ps (__m128 s, __mmask8 k, __m128 a, __m128 b); VSUBPS __m128 _mm_maskz_sub_ps (__mmask16 k, __m128 a, __m128 b);