blcmsk
Bit Line Create Mask
Creates mask from lowest clear bit (x ^ (x+1)).
Pseudocode Operation
result ← src ^ (src + 1); dest ← result; ZF ← (result == 0); SF ← result[31]; CF ← undefined; OF ← undefined; PF ← undefined;Example
Encoding
Operands
-
dest
32-bit general-purpose register (e.g. EAX) -
src
32-bit register or memory
Related
More in TBM
Reference
Instruction Forms
| Opcode | Instruction | Op/En | 64/32-bit Mode | CPUID | Description |
|---|---|---|---|---|---|
| 8F RXB.09 0.dest.0.00 02 /1 | BLCMSK reg32, reg/mem32 | ||||
| 8F RXB.09 1.dest.0.00 02 /1 | BLCMSK reg64, reg/mem64 |
Description
Finds the least significant zero bit in the source operand, sets that bit to 1, clears all bits above that bit to 0 and writes the result to the destination. If there is no zero bit in the source operand, the destination is written with all ones. This instruction has two operands: BLCMSK dest, src In 64-bit mode, the operand size is determined by the value of XOP.W. If XOP.W is 1, the operand size is 64-bit; if XOP.W is 0, the operand size is 32-bit. In 32-bit mode, XOP.W is ignored. 16-bit operands are not supported. The destination (dest) is a general purpose register. The source operand (src) is a general purpose register or a memory operand. The BLCMSK instruction effectively performs a bit-wise logical xor of the source operand and the result of incrementing the source operand by 1 and stores the result to the destination register: add tmp1, src, 1 xor dest, tmp1,src The value of the carry flag of rFLAGS is generated according to the result of the add pseudoinstruction and the remaining arithmetic flags are generated by the xor pseudo-instruction. If the input is all ones, the output is a value with all bits set to 1. The BLCMSK instruction is a TBM instruction. Support for this instruction is indicated by CPUID Fn8000_0001_ECX[TBM] = 1. For more information on using the CPUID instruction, see the instruction reference page for the CPUID instruction on page 165. For a description of all feature flags related to instruction subset support, see Appendix D, “Instruction Subsets and CPUID Feature Flags,” on page 593. Instruction Encoding