vpmacsww

Vector Packed Multiply Accumulate Signed Word

VPMACSWW xmm1, xmm2, xmm3, xmm4

Multiply-accumulate signed words.

Details

Multiplies pairs of signed 16-bit integers, accumulates the 32-bit products, and stores results in the destination XMM register without saturation. This is a 4-operand instruction encoding multiply-accumulate semantics: dest = src1 * src2 + src3. No flags are affected.

Pseudocode Operation

for i = 0 to 7:
  product ← sign_extend_32(src1[i*16:(i*16)+15]) *
            sign_extend_32(src2[i*16:(i*16)+15])
  result[i*32:(i*32)+31] ← product + sign_extend_32(src3[i*16:(i*16)+15])
dest ← result

Example

VPMACSWW xmm1, xmm2, xmm3, xmm4

Encoding

Binary Layout
VEX
+0
opcode
+3
ModRM
+4
 
Format XOP
Opcode XOP.128.08.W0 95 /r ib
Extension XOP

Operands

  • dest
    128-bit XMM SIMD register
  • src1
    128-bit XMM SIMD register
  • src2
    128-bit XMM SIMD register
  • src3
    128-bit XMM SIMD register

Reference (AMD APM)

Instruction Forms

Opcode Instruction Op/En 64/32-bit Mode CPUID Description
8F RXB.08 0.src1.0.00 95 /r ib VPMACSWW xmm1, xmm2, xmm3/mem128, xmm4

Description

Signed Word to Signed Word Multiplies each packed 16-bit signed integer value of the first source by the corresponding value of the second source, then adds the corresponding packed 16-bit signed integer value of the third source to each 32-bit signed integer product. Writes eight 16-bit results to the destination. No saturation is performed on the sum. When the result of the multiplication causes non-zero values to be set in the upper 16 bits of the 32 bit result, they are ignored. When the result of the add overflows, the carry is ignored (neither the overflow nor carry bit in rFLAGS is set). In both cases, only the signed low-order 16 bits of the result are written to the destination. There are four operands: VPMACSWW dest, src1, src2, src3 dest = src1* src2 + src3 The destination (dest) is an XMM register specified by ModRM.reg. When the destination XMM register is written, bits [255:128] of the corresponding YMM register are cleared. The first source (src1) is an XMM register specified by XOP.vvvv; the second source (src2) is either an XMM register or a 128-bit memory location specified by the ModRM.r/m field; and the third source (src3) is an XMM register specified by bits [7:4] of an immediate byte operand. When src3 designates the same XMM register as the dest register, the XMM register behaves as an accumulator.

Flags Affected

None None

Exceptions

Exceptions

Mode Exception Cause of Exception Real Virt Prot X Instruction not supported, as indicated by CPUID feature identifier. X X XOP instructions are only recognized in protected mode. X CR4.OSXSAVE = 0, indicated by CPUID Fn0000_0001_ECX[OSXSAVE]. X XFEATURE_ENABLED_MASK[2:1] ! = 11b. Invalid opcode, #UD X XOP.W = 1. X XOP.L = 1. X REX, F2, F3, or 66 prefix preceding XOP prefix. X Lock prefix (F0h) preceding opcode. Device not available, #NM X CR0.TS = 1. Stack, #SS X Memory address exceeding stack segment limit or non-canonical. X Memory address exceeding data segment limit or non-canonical. General protection, #GP X Null data segment used to reference memory. Page fault, #PF X Instruction execution caused a page fault. Alignment check, #AC X Memory operand not 16-byte aligned when alignment checking enabled. X — XOP exception 810 [AMDVPMACSWWPublic Use] Instruction Reference