kshiftrw

Shift Right Mask Word

KSHIFTRW k1, k2, imm8

Logically shifts 16-bit mask right.

Details

Logically shifts the 16-bit contents of the source k-register right by the count specified in an 8-bit immediate, storing the result in the destination k-register. Vacated bit positions are filled with zeros; bits shifted out are discarded. No flags are affected by this mask shift operation.

Pseudocode Operation

shift_count ← imm8 & 0x0F
k1 ← k2 >> shift_count
k1[16:63] ← 0

Example

KSHIFTRW k1, k2, 3

Encoding

Binary Layout
EVEX
+0
66
+4
0F
+5
3A
+6
32
+7
 
Format EVEX
Opcode VEX.L0.66.0F3A.W1 30 /r
Extension AVX-512F

Operands

  • dest
    AVX-512 opmask register (k0-k7)
  • src1
    AVX-512 opmask register (k0-k7)
  • src2
    8-bit signed immediate

Reference (Intel® SDM)

Instruction Forms

Opcode Instruction Op/En 64/32-bit Mode CPUID Description
VEX.L0.66.0F3A.W1 30 /r KSHIFTRW k1, k2, imm8 V/V RRI AVX512F OR AVX10.1 Shift right 16 bits in k2 by immediate and write result in k1.
VEX.L0.66.0F3A.W0 30 /r KSHIFTRB k1, k2, imm8 V/V RRI AVX512DQ OR AVX10.1 Shift right 8 bits in k2 by immediate and write result in k1.
VEX.L0.66.0F3A.W1 31 /r KSHIFTRQ k1, k2, imm8 V/V RRI AVX512BW OR AVX10.1 Shift right 64 bits in k2 by immediate and write result in k1.
VEX.L0.66.0F3A.W0 31 /r KSHIFTRD k1, k2, imm8 V/V RRI AVX512BW OR AVX10.1 Shift right 32 bits in k2 by immediate and write result in k1.

Description

Shifts 8/16/32/64 bits in the second operand (source operand) right by the count specified in immediate and place the least significant 8/16/32/64 bits of the result in the destination operand. The higher bits of the destination are zero-extended. The destination is set to zero if the count value is greater than 7 (for byte shift), 15 (for word shift), 31 (for doubleword shift) or 63 (for quadword shift).

Operation

KSHIFTRW
COUNT := imm8[7:0]
DEST[MAX_KL-1:0] := 0
IF COUNT <=15
THEN DEST[15:0] := SRC1[15:0] >> COUNT;
FI;

KSHIFTRB
COUNT := imm8[7:0]
DEST[MAX_KL-1:0] := 0
IF COUNT <=7
THEN   DEST[7:0] := SRC1[7:0] >> COUNT;
FI;

KSHIFTRQ
COUNT := imm8[7:0]
DEST[MAX_KL-1:0] := 0
IF COUNT <=63
THEN   DEST[63:0] := SRC1[63:0] >> COUNT;
FI;





KSHIFTRW/KSHIFTRB/KSHIFTRQ/KSHIFTRD—Shift Right Mask Registers                                                                      Vol. 2A 3-525
KSHIFTRD
COUNT := imm8[7:0]
DEST[MAX_KL-1:0] := 0
IF COUNT <=31
THEN   DEST[31:0] := SRC1[31:0] >> COUNT;
FI;

Intel C/C++ Compiler Intrinsic Equivalent

Compiler auto generates KSHIFTRW when needed.

Flags Affected

None.

Exceptions

SIMD Floating-Point Exceptions

None.

Other Exceptions

See Table 2-65, “TYPE K20 Exception Definition (VEX-Encoded OpMask Instructions w/o Memory Arg).” KSHIFTRW/KSHIFTRB/KSHIFTRQ/KSHIFTRD—Shift Right Mask Registers Vol. 2A 3-526