vaesenc
Vector AES Encrypt (AVX512)
AES Encrypt on 512-bit vector.
Pseudocode Operation
for block = 0 to 3:
state_128 ← zmm2[128*block:128*block+127]
round_key_128 ← zmm3/m512[128*block:128*block+127]
state_128 ← AES_SubBytes(state_128)
state_128 ← AES_ShiftRows(state_128)
state_128 ← AES_MixColumns(state_128)
state_128 ← state_128 XOR round_key_128
zmm1[128*block:128*block+127] ← state_128Encoding
Operands
-
dest
512-bit ZMM AVX-512 register -
src1
512-bit ZMM AVX-512 register -
src2
512-bit ZMM AVX-512 register or Memory operand
Related
More in AVX-512-VAES
Reference
Instruction Forms
| Opcode | Instruction | Op/En | 64/32-bit Mode | CPUID | Description |
|---|---|---|---|---|---|
| 66 0F 38 DC /r | AESENC xmm1, xmm2/m128 | A | V/V | AES | Perform one round of an AES encryption flow, using one 128-bit data (state) from xmm1 with one 128-bit round key from xmm2/m128. |
| VEX.128.66.0F38.WIG DC /r | VAESENC xmm1, xmm2, xmm3/m128 | B | V/V | AES AVX | Perform one round of an AES encryption flow, using one 128-bit data (state) from xmm2 with one 128-bit round key from the xmm3/m128; store the result in xmm1. |
| VEX.256.66.0F38.WIG DC /r | VAESENC ymm1, ymm2, ymm3/m256 | B | V/V | VAES | Perform one round of an AES encryption flow, using two 128-bit data (state) from ymm2 with two 128-bit round keys from the ymm3/m256; store the result in ymm1. |
| EVEX.128.66.0F38.WIG DC /r | VAESENC xmm1, xmm2, xmm3/m128 | C | V/V | VAES (AVX512VL OR AVX10.1) | Perform one round of an AES encryption flow, using one 128-bit data (state) from xmm2 with one 128-bit round key from the xmm3/m128; store the result in xmm1. |
| EVEX.256.66.0F38.WIG DC /r | VAESENC ymm1, ymm2, ymm3/m256 | C | V/V | VAES (AVX512VL OR AVX10.1) | Perform one round of an AES encryption flow, using two 128-bit data (state) from ymm2 with two 128-bit round keys from the ymm3/m256; store the result in ymm1. |
| EVEX.512.66.0F38.WIG DC /r | VAESENC zmm1, zmm2, zmm3/m512 | C | V/V | VAES (AVX512F OR AVX10.1) | Perform one round of an AES encryption flow, using four 128-bit data (state) from zmm2 with four 128-bit round keys from the zmm3/m512; store the result in zmm1. |
Instruction Operand Encoding
| Op/En | Tuple Type | Operand 1 | Operand 2 | Operand 3 | Operand 4 |
|---|---|---|---|---|---|
| A | N/A | ModRM:reg (r, w) | ModRM:r/m (r) | N/A | N/A |
| B | N/A | ModRM:reg (w) | VEX.vvvv (r) | ModRM:r/m (r) | N/A |
| C | Full Mem | ModRM:reg (w) | EVEX.vvvv (r) | ModRM:r/m (r) | N/A |
Description
This instruction performs a single round of an AES encryption flow using one/two/four (depending on vector length) 128-bit data (state) from the first source operand with one/two/four (depending on vector length) round key(s) from the second source operand, and stores the result in the destination operand. Use the AESENC instruction for all but the last encryption rounds. For the last encryption round, use the AESENCCLAST instruction. VEX and EVEX encoded versions of the instruction allow 3-operand (non-destructive) operation. The legacy encoded versions of the instruction require that the first source operand and the destination operand are the same and must be an XMM register. The EVEX encoded form of this instruction does not support memory fault suppression.
Operation
AESENC STATE := SRC1; RoundKey := SRC2; STATE := ShiftRows( STATE ); STATE := SubBytes( STATE ); STATE := MixColumns( STATE ); DEST[127:0] := STATE XOR RoundKey; DEST[MAXVL-1:128] (Unmodified) VAESENC (128b and 256b VEX Encoded Versions) (KL,VL) = (1,128), (2,256) FOR I := 0 to KL-1: STATE := SRC1.xmm[i] RoundKey := SRC2.xmm[i] STATE := ShiftRows( STATE ) STATE := SubBytes( STATE ) STATE := MixColumns( STATE ) DEST.xmm[i] := STATE XOR RoundKey DEST[MAXVL-1:VL] := 0 VAESENC (EVEX Encoded Version) (KL,VL) = (1,128), (2,256), (4,512) FOR i := 0 to KL-1: STATE := SRC1.xmm[i] // xmm[i] is the i’th xmm word in the SIMD register RoundKey := SRC2.xmm[i] STATE := ShiftRows( STATE ) STATE := SubBytes( STATE ) STATE := MixColumns( STATE ) DEST.xmm[i] := STATE XOR RoundKey DEST[MAXVL-1:VL] := 0
Intel C/C++ Compiler Intrinsic Equivalent
(V)AESENC __m128i _mm_aesenc (__m128i, __m128i) VAESENC __m256i _mm256_aesenc_epi128(__m256i, __m256i); VAESENC __m512i _mm512_aesenc_epi128(__m512i, __m512i);