vreducess

Perform Reduction Transformation Scalar Single

VREDUCESS xmm1 {k1}, xmm2, xmm3/m32, imm8

Performs reduction on low float.

Details

The Perform Reduction Transformation Scalar Single instruction performs reduction on low float.

Pseudocode Operation

// Performs reduction on low float

Example

VREDUCESS xmm1, xmm2, xmm3/m32, 3

Encoding

Binary Layout
EVEX
+0
66
+4
0F
+5
3A
+6
57
+7
 
Format EVEX
Opcode 66 0F 3A 57
Extension AVX-512DQ

Operands

  • dest
    128-bit XMM SIMD register
  • src1
    128-bit XMM SIMD register
  • src2
    128-bit XMM SIMD register or Memory operand
  • src3
    8-bit signed immediate