pext

Parallel Bits Extract

PEXT r32, r32, r/m32

Extracts bits from source using mask and packs them to LSB.

Details

Parallel Bits Extract copies bits from the first source operand to the destination at positions where the mask operand has set bits, compacting them toward the LSB. No flags are modified. Supported in 32-bit and 64-bit modes with BMI2 extension; operand size can be 32 or 64 bits.

Pseudocode Operation

result ← 0; dest_bit ← 0; for (i = 0; i < operand_size; i++) { if (src2[i]) { result[dest_bit] ← src1[i]; dest_bit += 1; } } dest ← result;

Example

PEXT eax, eax, ebx

Encoding

Binary Layout
VEX
+0
opcode
+3
ModRM
+4
 
Format VEX
Opcode VEX.LZ.F3.0F38.W0 F5 /r
Extension BMI2

Operands

  • dest
    32-bit general-purpose register (e.g. EAX)
  • src1
    32-bit general-purpose register (e.g. EAX)
  • src2
    32-bit register or memory

Reference (Intel® SDM)

Instruction Forms

Opcode Instruction Op/En 64/32-bit Mode CPUID Description
VEX.LZ.F3.0F38.W0 F5 /r PEXT r32a, r32b, r/m32 RVM V/V BMI2 Parallel extract of bits from r32b using mask in r/m32, result is written to r32a.
VEX.LZ.F3.0F38.W1 F5 /r PEXT r64a, r64b, r/m64 RVM V/N.E. BMI2 Parallel extract of bits from r64b using mask in r/m64, result is written to r64a.

Description

PEXT uses a mask in the second source operand (the third operand) to transfer either contiguous or non-contiguous bits in the first source operand (the second operand) to contiguous low order bit positions in the destination (the first operand). For each bit set in the MASK, PEXT extracts the corresponding bits from the first source operand and writes them into contiguous lower bits of destination operand. The remaining upper bits of destination are zeroed. SRC1 S31 S30 S29 S28 S27 S7 S6 S5 S4 S3 S2 S1 S0 SRC2 0 0 0 1 0 1 0 1 0 0 1 0 0 (mask) DEST 0 0 0 0 0 0 0 0 0 S28 S7 S5 S2 bit 31 bit 0 Figure 4-9. PEXT Example This instruction is not supported in real mode and virtual-8086 mode. The operand size is always 32 bits if not in 64-bit mode. In 64-bit mode operand size 64 requires VEX.W1. VEX.W1 is ignored in non-64-bit modes. An attempt to execute this instruction with VEX.L not equal to 0 will cause #UD. PEXT—Parallel Bits Extract Vol. 2B 4-284

Operation

TEMP := SRC1;
MASK := SRC2;
DEST := 0 ;
m := 0, k := 0;
DO WHILE m < OperandSize

IF MASK[ m] = 1 THEN
DEST[ k] := TEMP[ m];
k := k+ 1;
FI
m := m+ 1;

OD

Intel C/C++ Compiler Intrinsic Equivalent

PEXT unsigned __int32 _pext_u32(unsigned __int32 src, unsigned __int32 mask);
PEXT unsigned __int64 _pext_u64(unsigned __int64 src, unsigned __int32 mask);

Flags Affected

None.

Exceptions

SIMD Floating-Point Exceptions

None.

Other Exceptions

See Table 2-29, “Type 13 Class Exception Conditions.” PEXT—Parallel Bits Extract Vol. 2B 4-285