vpshab
Vector Packed Shift Arithmetic Byte
VPSHAB xmm1, xmm2/m128, xmm3
Shifts bytes arithmetically.
Details
Performs arithmetic left or right shift on each byte element within a 128-bit XMM register based on the 8-bit signed immediate, with positive values for left shift and negative for right shift (sign-extending). This XOP instruction does not modify CPU flags.
Pseudocode Operation
for i in 0..15:
if (imm8 >= 0):
xmm1[i*8+7:i*8] ← src1[i*8+7:i*8] << (imm8 & 7)
else:
xmm1[i*8+7:i*8] ← arithmetic_shift_right(src1[i*8+7:i*8], (-imm8) & 7)Example
VPSHAB xmm1, xmm2/m128, 3
Encoding
Binary Layout
VEX
+0
opcode
+3
ModRM
+4
Operands
-
dest
128-bit XMM SIMD register -
src1
128-bit XMM SIMD register or Memory operand -
src2
8-bit signed immediate
Reference (AMD APM)
Instruction Forms
| Opcode | Instruction | Op/En | 64/32-bit Mode | CPUID | Description |
|---|---|---|---|---|---|
| 8F RXB.09 0.count.0.00 98 /r | VPSHAB xmm1, xmm2/mem128, xmm3 | ||||
| 8F RXB.09 1.src.0.00 98 /r | VPSHAB xmm1, xmm2, xmm3/mem128 |
Description
Bytes
Shifts each signed byte of the source as specified by a count byte and writes the result to the corresponding byte of the destination.
The count bytes are 8-bit signed two's-complement values in the corresponding bytes of the count operand.
When the count value is positive, bits are shifted to the left (toward the more significant bit positions).
Zeros are shifted in at the right end (least-significant bit) of the byte.
When the count value is negative, bits are shifted to the right (toward the least significant bit positions). The most significant bit (sign bit) is replicated and shifted in at the left end (most-significant bit) of the byte.
There are three operands: VPSHAB dest, src, count
The destination (dest) is an XMM register specified by ModRM.reg.
Both src and count are configured by XOP.W.
• When XOP.W = 0, count is an XMM register specified by XOP.vvvv and src is either an XMM register or a128-bit memory location specified by ModRM.r/m.
• When XOP.W = 1, count is either an XMM register or a 128-bit memory location specified by
ModRM.r/m and src is an XMM register specified by XOP.vvvv.
Bits [255:128] of the YMM register that corresponds to the destination are cleared.
Flags Affected
None None
Exceptions
Exceptions
Mode
Exception Cause of Exception
Real Virt Prot
X Instruction not supported, as indicated by CPUID feature identifier.
X X XOP instructions are only recognized in protected mode.
X CR4.OSXSAVE = 0, indicated by CPUID Fn0000_0001_ECX[OSXSAVE].
Invalid opcode, #UD X XFEATURE_ENABLED_MASK[2:1] ! = 11b.
X XOP.L = 1.
X REX, F2, F3, or 66 prefix preceding XOP prefix.
X Lock prefix (F0h) preceding opcode.
Device not available, #NM X CR0.TS = 1.
Stack, #SS X Memory address exceeding stack segment limit or non-canonical.
X Memory address exceeding data segment limit or non-canonical.
General protection, #GP
X Null data segment used to reference memory.
Page fault, #PF X Instruction execution caused a page fault.
Alignment check, #AC X Memory operand not 16-byte aligned when alignment checking enabled.
X — XOP exception
830 [AMD VPSHABPublic Use] Instruction Reference