vdivsh

Divide Scalar Half-Precision

VDIVSH xmm1 {k1}, xmm2, xmm3/m16

Divides low FP16 value.

Details

Divides the low-order half-precision (FP16) element of the first operand by the second and stores the scalar result in the low 16 bits of the destination, with upper 112 bits cleared or preserved based on write-mask. Uses EVEX encoding with optional masking and exception suppression. Rounding controlled by MXCSR[15:13]; may generate precision/underflow/overflow exceptions.

Pseudocode Operation

if (k1[0] || !masking_enabled) {
  dest[0:15] ← src1[0:15] ÷FP16 src2[0:15];
} else {
  dest[0:15] ← preserve_or_zero(dest[0:15]);
}
dest[16:127] ← 0;

Example

VDIVSH xmm1, xmm2, xmm3/m16

Encoding

Binary Layout
EVEX
+0
5E
+4
 
Format EVEX
Opcode EVEX.LLIG.F3.MAP5.W0 5E /r
Extension AVX-512-FP16

Operands

  • dest
    128-bit XMM SIMD register
  • src1
    128-bit XMM SIMD register
  • src2
    128-bit XMM SIMD register or Memory operand

Reference (Intel® SDM)

Instruction Forms

Opcode Instruction Op/En 64/32-bit Mode CPUID Description
EVEX.LLIG.F3.MAP5.W0 5E /r VDIVSH xmm1{k1}{z}, xmm2, xmm3/m16 {er} A V/V AVX512_FP16 OR AVX10.1 Divide low FP16 value in xmm2 by low FP16 value in xmm3/m16, and store the result in xmm1 subject to writemask k1. Bits 127:16 of xmm2 are copied to xmm1[127:16].

Instruction Operand Encoding

Op/En Tuple Type Operand 1 Operand 2 Operand 3 Operand 4
A Scalar ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) N/A

Description

This instruction divides the low FP16 value from the first source operand by the corresponding value in the second source operand, storing the FP16 result in the destination operand. Bits 127:16 of the destination operand are copied from the corresponding bits of the first source operand. Bits MAXVL-1:128 of the destination operand are zeroed. The low FP16 element of the destination is updated according to the writemask.

Operation

VDIVSH (EVEX Encoded Versions)
IF EVEX.b = 1 and SRC2 is a register:
SET_RM(EVEX.RC)
ELSE
SET_RM(MXCSR.RC)

IF k1[0] OR *no writemask*:
DEST.fp16[0] := SRC1.fp16[0] / SRC2.fp16[0]
ELSE IF *zeroing*:
DEST.fp16[0] := 0
// else dest.fp16[0] remains unchanged

DEST[127:16] := SRC1[127:16]
DEST[MAXVL-1:128] := 0

Intel C/C++ Compiler Intrinsic Equivalent

VDIVSH __m128h _mm_div_round_sh (__m128h a, __m128h b, int rounding);
VDIVSH __m128h _mm_mask_div_round_sh (__m128h src, __mmask8 k, __m128h a, __m128h b, int rounding);
VDIVSH __m128h _mm_maskz_div_round_sh (__mmask8 k, __m128h a, __m128h b, int rounding);
VDIVSH __m128h _mm_div_sh (__m128h a, __m128h b);
VDIVSH __m128h _mm_mask_div_sh (__m128h src, __mmask8 k, __m128h a, __m128h b);
VDIVSH __m128h _mm_maskz_div_sh (__mmask8 k, __m128h a, __m128h b);

Exceptions

SIMD Floating-Point Exceptions

Invalid, Underflow, Overflow, Precision, Denormal, Zero.

Other Exceptions

EVEX-encoded instructions, see Table 2-49, “Type E3 Class Exception Conditions.” VDIVSH—Divide Scalar FP16 Values Vol. 2C 5-159