vsm3msg1

SM3 Message Schedule 1

VSM3MSG1 xmm1, xmm2, xmm3

SM3 crypto message schedule part 1.

Details

Performs the first stage of SM3 (Chinese cryptographic hash standard) message schedule computation on 128-bit inputs, producing a 128-bit expanded message word. This instruction combines three XMM operands using SM3-specific expansion logic and does not modify EFLAGS.

Pseudocode Operation

W ← xmm2[32*i..32*i+31] for i in 0 to 3
W_prime ← xmm3[32*i..32*i+31] for i in 0 to 3
W_new ← sm3_msg1_expand(W, W_prime)
xmm1[128 bits] ← W_new

Example

VSM3MSG1 xmm1, xmm2, xmm3

Encoding

Binary Layout
DA
+0
 
Format VEX
Opcode VEX.128.NP.0F38.W0 DA /r
Extension SM3

Operands

  • dest
    128-bit XMM SIMD register
  • src1
    128-bit XMM SIMD register
  • src2
    128-bit XMM SIMD register

Reference (Intel® SDM)

Instruction Forms

Opcode Instruction Op/En 64/32-bit Mode CPUID Description
VEX.128.NP.0F38.W0 DA /r VSM3MSG1 xmm1, xmm2, xmm3/m128 A V/V AVX SM3 Performs an initial calculation for the next four SM3 message words using previous message words from xmm2 and xmm3/m128, storing the result in xmm1.

Instruction Operand Encoding

Op/En Tuple Type Operand 1 Operand 2 Operand 3 Operand 4
A N/A ModRM:reg (r, w) VEX.vvvv (r) ModRM:r/m (r) N/A

Description

The VSM3MSG1 instruction is one of the two SM3 message scheduling instructions. The instruction performs an initial calculation for the next four SM3 message words.

Operation

define ROL32(dword, n):
count := n % 32
dest := (dword << count) | (dword >> (32-count))
return dest

define P1(x):
return x ^ ROL32(x, 15) ^ ROL32(x, 23)

VSM3MSG1 SRCDEST, SRC1, SRC2
W[0] := SRC2.dword[0]
W[1] := SRC2.dword[1]
W[2] := SRC2.dword[2]
W[3] := SRC2.dword[3]

W[7] := SRCDEST.dword[0]
W[8] := SRCDEST.dword[1]
W[9] := SRCDEST.dword[2]
W[10] := SRCDEST.dword[3]

W[13] := SRC1.dword[0]
W[14] := SRC1.dword[1]
W[15] := SRC1.dword[2]

TMP0 := W[7] ^ W[0] ^ ROL32(W[13], 15)
TMP1 := W[8] ^ W[1] ^ ROL32(W[14], 15)
TMP2 := W[9] ^ W[2] ^ ROL32(W[15], 15)
TMP3 := W[10] ^ W[3]

SRCDEST.dword[0] := P1(TMP0)
SRCDEST.dword[1] := P1(TMP1)
SRCDEST.dword[2] := P1(TMP2)
SRCDEST.dword[3] := P1(TMP3)




VSM3MSG1—Perform Initial Calculation for the Next Four SM3 Message Words                                                                Vol. 2C 5-755

Intel C/C++ Compiler Intrinsic Equivalent

VSM3MSG1 __m128i _mm_sm3msg1_epi32 (__m128i __A, __m128i __B, __m128i __C);

Flags Affected

None.

Exceptions

SIMD Floating-Point Exceptions

None.

Other Exceptions

See Table 2-21, “Type 4 Class Exception Conditions.” VSM3MSG1—Perform Initial Calculation for the Next Four SM3 Message Words Vol. 2C 5-756