shufps

Shuffle Packed Single-Precision

SHUFPS xmm1, xmm2/m128, imm8

Shuffles 32-bit floats between two XMM registers.

Details

The Shuffle Packed Single-Precision instruction shuffles 32-bit floats between two XMM registers.

Pseudocode Operation

// Shuffles 32-bit floats between two XMM registers

Example

SHUFPS xmm1, xmm2/m128, 3

Encoding

Binary Layout
0F
+0
C6
+1
 
Format SSE
Opcode 0F C6
Extension SSE

Operands

  • dest
    128-bit XMM SIMD register
  • src1
    128-bit XMM SIMD register or Memory operand
  • src2
    8-bit signed immediate