crc32

Accumulate CRC32 Value

CRC32 r32, r/m

Accumulates CRC32C value using polynomial 0x11EDC6F41.

Pseudocode Operation

if Src is 8-bit:
  Dest[0..31] ← CRC32C(Dest[0..31], [Src])
  Dest[32..63] ← 0 (if 64-bit destination)
else if Src is 16-bit:
  Dest[0..31] ← CRC32C(Dest[0..31], [Src])
  Dest[32..63] ← 0 (if 64-bit destination)
else if Src is 32-bit:
  Dest[0..31] ← CRC32C(Dest[0..31], [Src])
  Dest[32..63] ← 0 (if 64-bit destination)
else if Src is 64-bit:
  Dest ← CRC32C(Dest, [Src])

Example

CRC32 eax, rbx

Encoding

Binary Layout

Format SSE4.2

Opcode F2 0F 38 F1

Extension SSE4.2

Operands

dest
32-bit general-purpose register (e.g. EAX)
src
Register or memory operand

Reference

View in Intel® 64 and IA-32 Architectures SDM ↗ Intel® SDM

Instruction Forms

Opcode	Instruction	Op/En	64/32-bit Mode	Description
F2 0F 38 F0 /r	CRC32 r32, r/m8	RM	Valid Valid	Accumulate CRC32 on r/m8.
F2 0F 38 F1 /r	CRC32 r32, r/m16	RM	Valid Valid	Accumulate CRC32 on r/m16.
F2 0F 38 F1 /r	CRC32 r32, r/m32	RM	Valid Valid	Accumulate CRC32 on r/m32.
F2 REX.W 0F 38 F0 /r	CRC32 r64, r/m8	RM	Valid N.E.	Accumulate CRC32 on r/m8.
F2 REX.W 0F 38 F1 /r	CRC32 r64, r/m64	RM	Valid N.E.	Accumulate CRC32 on r/m64.

Description

Starting with an initial value in the first operand (destination operand), accumulates a CRC32 (polynomial 11EDC6F41H) value for the second operand (source operand) and stores the result in the destination operand. The source operand can be a register or a memory location. The destination operand must be an r32 or r64 register. If the destination is an r64 register, then the 32-bit result is stored in the least significant double word and 00000000H is stored in the most significant double word of the r64 register. The initial value supplied in the destination operand is a double word integer stored in the r32 register or the least significant double word of the r64 register. To incrementally accumulate a CRC32 value, software retains the result of the previous CRC32 operation in the destination operand, then executes the CRC32 instruction again with new input data in the source operand. Data contained in the source operand is processed in reflected bit order. This means that the most significant bit of the source operand is treated as the least significant bit of the quotient, and so on, for all the bits of the source operand. Likewise, the result of the CRC operation is stored in the destination operand in reflected bit order. This means that the most significant bit of the resulting CRC (bit 31) is stored in the least significant bit of the destination operand (bit 0), and so on, for all the bits of the CRC.

Intel C/C++ Compiler Intrinsic Equivalent

unsigned int _mm_crc32_u8( unsigned int crc, unsigned char data )
unsigned int _mm_crc32_u16( unsigned int crc, unsigned short data )
unsigned int _mm_crc32_u32( unsigned int crc, unsigned int data )
unsigned __int64 _mm_crc32_u64( unsigned __int64 crc, unsigned __int64 data )

Flags Affected

None. CRC32-Accumulate CRC32 Value Vol. 2A 3-206

Exceptions

SIMD Floating-Point Exceptions

None.

Protected Mode Exceptions

#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS or GS segments. #SS(0) If a memory operand effective address is outside the SS segment limit. #PF (fault-code) For a page fault. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. #UD If CPUID.01H:ECX.SSE4_2[20] = 0. If LOCK prefix is used.

Real-Address Mode Exceptions

#GP(0) If any part of the operand lies outside of the effective address space from 0 to 0FFFFH. #SS(0) If a memory operand effective address is outside the SS segment limit. #UD If CPUID.01H:ECX.SSE4_2[20] = 0. If LOCK prefix is used. Virtual 8086 Mode Exceptions #GP(0) If any part of the operand lies outside of the effective address space from 0 to 0FFFFH. #SS(0) If a memory operand effective address is outside the SS segment limit. #PF (fault-code) For a page fault. #AC(0) If alignment checking is enabled and an unaligned memory reference is made. #UD If CPUID.01H:ECX.SSE4_2[20] = 0. If LOCK prefix is used.

Compatibility Mode Exceptions

Same exceptions as in Protected Mode.

64-Bit Mode Exceptions

#GP(0) If the memory address is in a non-canonical form. #SS(0) If a memory address referencing the SS segment is in a non-canonical form. #PF (fault-code) For a page fault. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. #UD If CPUID.01H:ECX.SSE4_2[20] = 0. If LOCK prefix is used. CRC32-Accumulate CRC32 Value Vol. 2A 3-207