vpcmpuq
Compare Packed Unsigned Quadword Integers
VPCMPUQ k1 {k2}, zmm2, zmm3/m512, imm8
Compares unsigned quadwords and stores result in k-register.
Details
Compares packed unsigned 64-bit integers in zmm2 against zmm3/m512 using the comparison predicate in imm8, storing boolean results in opmask k1 (optionally merged with k2). Operates on 8 quadword elements in 512-bit vectors; all comparisons are unsigned and imm8 encodes the predicate (equal, less-than, less-equal, not-equal, etc.). Available in 64-bit mode with AVX-512F extension; EFLAGS remain unchanged.
Pseudocode Operation
for i in 0..7:
elem1 ← zmm2[64*i : 64*i+63] as unsigned 64-bit
elem2 ← zmm3/m512[64*i : 64*i+63] as unsigned 64-bit
k1[i] ← (mask_merge) ? k2[i] : 0
if pred(elem1, elem2, imm8) then k1[i] ← 1Example
VPCMPUQ k1, zmm2, zmm3/m512, 3
Encoding
Binary Layout
EVEX
+0
opcode
+4
ModRM
+5
Operands
-
dest
AVX-512 opmask register (k0-k7) -
src1
512-bit ZMM AVX-512 register -
src2
512-bit ZMM AVX-512 register or Memory operand -
src3
8-bit signed immediate
Reference (Intel® SDM)
Instruction Forms
| Opcode | Instruction | Op/En | 64/32-bit Mode | CPUID | Description |
|---|---|---|---|---|---|
| EVEX.128.66.0F3A.W1 1F /r ib | VPCMPQ k1 {k2}, xmm2, xmm3/m128/m64bcst, imm8 | A | V/V | (AVX512VL AND AVX512F) OR AVX10.1 | Compare packed signed quadword integer values in xmm3/m128/m64bcst and xmm2 using bits 2:0 of imm8 as a comparison predicate with writemask k2 and leave the result in mask register k1. |
| EVEX.256.66.0F3A.W1 1F /r ib | VPCMPQ k1 {k2}, ymm2, ymm3/m256/m64bcst, imm8 | A | V/V | (AVX512VL AND AVX512F) OR AVX10.1 | Compare packed signed quadword integer values in ymm3/m256/m64bcst and ymm2 using bits 2:0 of imm8 as a comparison predicate with writemask k2 and leave the result in mask register k1. |
| EVEX.512.66.0F3A.W1 1F /r ib | VPCMPQ k1 {k2}, zmm2, zmm3/m512/m64bcst, imm8 | A | V/V | AVX512F OR AVX10.1 | Compare packed signed quadword integer values in zmm3/m512/m64bcst and zmm2 using bits 2:0 of imm8 as a comparison predicate with writemask k2 and leave the result in mask register k1. |
| EVEX.128.66.0F3A.W1 1E /r ib | VPCMPUQ k1 {k2}, xmm2, xmm3/m128/m64bcst, imm8 | A | V/V | (AVX512VL AND AVX512F) OR AVX10.1 | Compare packed unsigned quadword integer values in xmm3/m128/m64bcst and xmm2 using bits 2:0 of imm8 as a comparison predicate with writemask k2 and leave the result in mask register k1. |
| EVEX.256.66.0F3A.W1 1E /r ib | VPCMPUQ k1 {k2}, ymm2, ymm3/m256/m64bcst, imm8 | A | V/V | (AVX512VL AND AVX512F) OR AVX10.1 | Compare packed unsigned quadword integer values in ymm3/m256/m64bcst and ymm2 using bits 2:0 of imm8 as a comparison predicate with writemask k2 and leave the result in mask register k1. |
| EVEX.512.66.0F3A.W1 1E /r ib | VPCMPUQ k1 {k2}, zmm2, zmm3/m512/m64bcst, imm8 | A | V/V | AVX512F OR AVX10.1 | Compare packed unsigned quadword integer values in zmm3/m512/m64bcst and zmm2 using bits 2:0 of imm8 as a comparison predicate with writemask k2 and leave the result in mask register k1. |
Instruction Operand Encoding
| Op/En | Tuple Type | Operand 1 | Operand 2 | Operand 3 | Operand 4 |
|---|---|---|---|---|---|
| A | Full | ModRM:reg (w) | EVEX.vvvv (r) | ModRM:r/m (r) | imm8 |
Description
Performs a SIMD compare of the packed integer values in the second source operand and the first source operand and returns the results of the comparison to the mask destination operand. The comparison predicate operand (immediate byte) specifies the type of comparison performed on each pair of packed values in the two source operands. The result of each comparison is a single mask bit result of 1 (comparison true) or 0 (comparison false).
VPCMPQ/VPCMPUQ performs a comparison between pairs of signed/unsigned quadword integer values.
The first source operand (second operand) is a ZMM/YMM/XMM register. The second source operand can be a
ZMM/YMM/XMM register or a 512/256/128-bit memory location or a 512-bit vector broadcasted from a 64-bit memory location. The destination operand (first operand) is a mask register k1. Up to 8/4/2 comparisons are performed with results written to the destination operand under the writemask k2.
The comparison predicate operand is an 8-bit immediate: bits 2:0 define the type of comparison to be performed.
Bits 3 through 7 of the immediate are reserved. Compiler can implement the pseudo-op mnemonic listed in Table
5-19.
VPCMPQ/VPCMPUQ—Compare Packed Integer Values Into Mask Vol. 2C 5-462
Operation
CASE (COMPARISON PREDICATE) OF 0: OP := EQ; 1: OP := LT; 2: OP := LE; 3: OP := FALSE; 4: OP := NEQ; 5: OP := NLT; 6: OP := NLE; 7: OP := TRUE; ESAC; VPCMPQ (EVEX encoded versions) (KL, VL) = (2, 128), (4, 256), (8, 512) FOR j := 0 TO KL-1 i := j * 64 IF k2[j] OR *no writemask* THEN IF (EVEX.b = 1) AND (SRC2 *is memory*) THEN CMP := SRC1[i+63:i] OP SRC2[63:0]; ELSE CMP := SRC1[i+63:i] OP SRC2[i+63:i]; FI; IF CMP = TRUE THEN DEST[j] := 1; ELSE DEST[j] := 0; FI; ELSE DEST[j] := 0 ; zeroing-masking only FI; ENDFOR DEST[MAX_KL-1:KL] := 0 VPCMPUQ (EVEX encoded versions) (KL, VL) = (2, 128), (4, 256), (8, 512) FOR j := 0 TO KL-1 i := j * 64 IF k2[j] OR *no writemask* THEN IF (EVEX.b = 1) AND (SRC2 *is memory*) THEN CMP := SRC1[i+63:i] OP SRC2[63:0]; ELSE CMP := SRC1[i+63:i] OP SRC2[i+63:i]; FI; IF CMP = TRUE THEN DEST[j] := 1; ELSE DEST[j] := 0; FI; ELSE DEST[j] := 0 ; zeroing-masking only FI; ENDFOR DEST[MAX_KL-1:KL] := 0 VPCMPQ/VPCMPUQ—Compare Packed Integer Values Into Mask Vol. 2C 5-463
Intel C/C++ Compiler Intrinsic Equivalent
VPCMPQ __mmask8 _mm512_cmp_epi64_mask( __m512i a, __m512i b, int imm); VPCMPQ __mmask8 _mm512_mask_cmp_epi64_mask(__mmask8 k, __m512i a, __m512i b, int imm); VPCMPQ __mmask8 _mm512_cmp[eq|ge|gt|le|lt|neq]_epi64_mask( __m512i a, __m512i b); VPCMPQ __mmask8 _mm512_mask_cmp[eq|ge|gt|le|lt|neq]_epi64_mask(__mmask8 k, __m512i a, __m512i b); VPCMPUQ __mmask8 _mm512_cmp_epu64_mask( __m512i a, __m512i b, int imm); VPCMPUQ __mmask8 _mm512_mask_cmp_epu64_mask(__mmask8 k, __m512i a, __m512i b, int imm); VPCMPUQ __mmask8 _mm512_cmp[eq|ge|gt|le|lt|neq]_epu64_mask( __m512i a, __m512i b); VPCMPUQ __mmask8 _mm512_mask_cmp[eq|ge|gt|le|lt|neq]_epu64_mask(__mmask8 k, __m512i a, __m512i b); VPCMPQ __mmask8 _mm256_cmp_epi64_mask( __m256i a, __m256i b, int imm); VPCMPQ __mmask8 _mm256_mask_cmp_epi64_mask(__mmask8 k, __m256i a, __m256i b, int imm); VPCMPQ __mmask8 _mm256_cmp[eq|ge|gt|le|lt|neq]_epi64_mask( __m256i a, __m256i b); VPCMPQ __mmask8 _mm256_mask_cmp[eq|ge|gt|le|lt|neq]_epi64_mask(__mmask8 k, __m256i a, __m256i b); VPCMPUQ __mmask8 _mm256_cmp_epu64_mask( __m256i a, __m256i b, int imm); VPCMPUQ __mmask8 _mm256_mask_cmp_epu64_mask(__mmask8 k, __m256i a, __m256i b, int imm); VPCMPUQ __mmask8 _mm256_cmp[eq|ge|gt|le|lt|neq]_epu64_mask( __m256i a, __m256i b); VPCMPUQ __mmask8 _mm256_mask_cmp[eq|ge|gt|le|lt|neq]_epu64_mask(__mmask8 k, __m256i a, __m256i b); VPCMPQ __mmask8 _mm_cmp_epi64_mask( __m128i a, __m128i b, int imm); VPCMPQ __mmask8 _mm_mask_cmp_epi64_mask(__mmask8 k, __m128i a, __m128i b, int imm); VPCMPQ __mmask8 _mm_cmp[eq|ge|gt|le|lt|neq]_epi64_mask( __m128i a, __m128i b); VPCMPQ __mmask8 _mm_mask_cmp[eq|ge|gt|le|lt|neq]_epi64_mask(__mmask8 k, __m128i a, __m128i b); VPCMPUQ __mmask8 _mm_cmp_epu64_mask( __m128i a, __m128i b, int imm); VPCMPUQ __mmask8 _mm_mask_cmp_epu64_mask(__mmask8 k, __m128i a, __m128i b, int imm); VPCMPUQ __mmask8 _mm_cmp[eq|ge|gt|le|lt|neq]_epu64_mask( __m128i a, __m128i b); VPCMPUQ __mmask8 _mm_mask_cmp[eq|ge|gt|le|lt|neq]_epu64_mask(__mmask8 k, __m128i a, __m128i b);
Exceptions
SIMD Floating-Point Exceptions
None
Other Exceptions
EVEX-encoded instruction, see Table 2-51, “Type E4 Class Exception Conditions.”
VPCMPQ/VPCMPUQ—Compare Packed Integer Values Into Mask Vol. 2C 5-464