vsqrtph

Square Root Packed FP16 Values

VSQRTPH zmm1 {k1}, zmm2/m512

Square root of half-precision values.

Details

Computes the square root of 32 half-precision (FP16) floating-point values from zmm2/m512, storing the result in zmm1 with optional write masking via k1. Square root follows IEEE 754 semantics with rounding controlled by MXCSR. Requires AVX-512-FP16 extension. Invalid operation (negative non-zero operand) and underflow/precision exceptions are reported via MXCSR.

Pseudocode Operation

for i ← 0 to 31 do
  if (k1[i] or no_mask) then
    zmm1[16*i+15:16*i] ← FP16_SQRT(zmm2[16*i+15:16*i]);
  else if (zeroing_mask)
    zmm1[16*i+15:16*i] ← 0;
endfor;
// MXCSR exception flags updated per result (invalid operation, underflow, etc.)

Example

VSQRTPH zmm1, zmm2/m512

Encoding

Binary Layout

EVEX

Format EVEX

Opcode EVEX.512.NP.MAP5.W0 51 /r

Extension AVX-512-FP16

Operands

dest
512-bit ZMM AVX-512 register
src
512-bit ZMM AVX-512 register or Memory operand

Reference (Intel® SDM)

Instruction Forms

Opcode	Instruction	Op/En	64/32-bit Mode	CPUID	Description
EVEX.128.NP.MAP5.W0 51 /r	VSQRTPH xmm1{k1}{z}, xmm2/m128/m16bcst	A	V/V	(AVX512_FP16 AND AVX512VL) OR AVX10.1	Compute square roots of the packed FP16 values in xmm2/m128/m16bcst, and store the result in xmm1 subject to writemask k1.
EVEX.256.NP.MAP5.W0 51 /r	VSQRTPH ymm1{k1}{z}, ymm2/m256/m16bcst	A	V/V	(AVX512_FP16 AND AVX512VL) OR AVX10.1	Compute square roots of the packed FP16 values in ymm2/m256/m16bcst, and store the result in ymm1 subject to writemask k1.
EVEX.512.NP.MAP5.W0 51 /r	VSQRTPH zmm1{k1}{z}, zmm2/m512/m16bcst {er}	A	V/V	AVX512_FP16 OR AVX10.1	Compute square roots of the packed FP16 values in zmm2/m512/m16bcst, and store the result in zmm1 subject to writemask k1.

Instruction Operand Encoding

Op/En	Tuple Type	Operand 1	Operand 2	Operand 3	Operand 4
A	Full	ModRM:reg (w)	ModRM:r/m (r)	N/A	N/A

Description

This instruction performs a packed FP16 square-root computation on the values from source operand and stores the packed FP16 result in the destination operand. The destination elements are updated according to the writemask.

Operation

VSQRTPH dest{k1}, src
VL = 128, 256 or 512
KL := VL/16

FOR i := 0 to KL-1:
IF k1[i] or *no writemask*:
IF SRC is memory and (EVEX.b = 1):
tsrc := src.fp16[0]
ELSE:
tsrc := src.fp16[i]
DEST.fp16[i] := SQRT(tsrc)
ELSE IF *zeroing*:
DEST.fp16[i] := 0
//else DEST.fp16[i] remains unchanged

DEST[MAXVL-1:VL] := 0





VSQRTPH—Compute Square Root of Packed FP16 Values                                                                                       Vol. 2C 5-765

Intel C/C++ Compiler Intrinsic Equivalent

VSQRTPH __m128h _mm_mask_sqrt_ph (__m128h src, __mmask8 k, __m128h a);
VSQRTPH __m128h _mm_maskz_sqrt_ph (__mmask8 k, __m128h a);
VSQRTPH __m128h _mm_sqrt_ph (__m128h a);
VSQRTPH __m256h _mm256_mask_sqrt_ph (__m256h src, __mmask16 k, __m256h a);
VSQRTPH __m256h _mm256_maskz_sqrt_ph (__mmask16 k, __m256h a);
VSQRTPH __m256h _mm256_sqrt_ph (__m256h a);
VSQRTPH __m512h _mm512_mask_sqrt_ph (__m512h src, __mmask32 k, __m512h a);
VSQRTPH __m512h _mm512_maskz_sqrt_ph (__mmask32 k, __m512h a);
VSQRTPH __m512h _mm512_sqrt_ph (__m512h a);
VSQRTPH __m512h _mm512_mask_sqrt_round_ph (__m512h src, __mmask32 k, __m512h a, const int rounding);
VSQRTPH __m512h _mm512_maskz_sqrt_round_ph (__mmask32 k, __m512h a, const int rounding);
VSQRTPH __m512h _mm512_sqrt_round_ph (__m512h a, const int rounding);

Exceptions

SIMD Floating-Point Exceptions

Invalid, Precision, Denormal.

Other Exceptions

EVEX-encoded instruction, see Table 2-48, “Type E2 Class Exception Conditions.” VSQRTPH—Compute Square Root of Packed FP16 Values Vol. 2C 5-766