kshiftlq

Shift Left Mask Quadword

KSHIFTLQ k1, k2, imm8

Logically shifts 64-bit mask left.

Details

Logically shifts the 64-bit content of the source mask register left by the amount specified in the immediate operand, storing the result in the destination mask register. Bits shifted out are discarded; vacant bit positions are filled with zeros. No flags are affected; this is an AVX-512BW instruction that operates only on opmask registers (k0–k7).

Pseudocode Operation

dest ← (src1 << imm8) & 0xFFFFFFFFFFFFFFFF;

Example

KSHIFTLQ k1, k2, 3

Encoding

Binary Layout

EVEX

Format EVEX

Opcode VEX.L0.66.0F3A.W1 33 /r

Extension AVX-512BW

Operands

dest
AVX-512 opmask register (k0-k7)
src1
AVX-512 opmask register (k0-k7)
src2
8-bit signed immediate

Reference (Intel® SDM)

Instruction Forms

Opcode	Instruction	64/32-bit Mode	CPUID	Description
VEX.L0.66.0F3A.W1 32 /r	KSHIFTLW k1, k2, imm8	V/V	RRI AVX512F OR AVX10.1	Shift left 16 bits in k2 by immediate and write result in k1.
VEX.L0.66.0F3A.W0 32 /r	KSHIFTLB k1, k2, imm8	V/V	RRI AVX512DQ OR AVX10.1	Shift left 8 bits in k2 by immediate and write result in k1.
VEX.L0.66.0F3A.W1 33 /r	KSHIFTLQ k1, k2, imm8	V/V	RRI AVX512BW OR AVX10.1	Shift left 64 bits in k2 by immediate and write result in k1.
VEX.L0.66.0F3A.W0 33 /r	KSHIFTLD k1, k2, imm8	V/V	RRI AVX512BW OR AVX10.1	Shift left 32 bits in k2 by immediate and write result in k1.

Description

Shifts 8/16/32/64 bits in the second operand (source operand) left by the count specified in immediate byte and place the least significant 8/16/32/64 bits of the result in the destination operand. The higher bits of the destination are zero-extended. The destination is set to zero if the count value is greater than 7 (for byte shift), 15 (for word shift), 31 (for doubleword shift) or 63 (for quadword shift).

Operation

KSHIFTLW
COUNT := imm8[7:0]
DEST[MAX_KL-1:0] := 0
IF COUNT <=15
THEN DEST[15:0] := SRC1[15:0] << COUNT;
FI;

KSHIFTLB
COUNT := imm8[7:0]
DEST[MAX_KL-1:0] := 0
IF COUNT <=7
THEN   DEST[7:0] := SRC1[7:0] << COUNT;
FI;

KSHIFTLQ
COUNT := imm8[7:0]
DEST[MAX_KL-1:0] := 0
IF COUNT <=63
THEN   DEST[63:0] := SRC1[63:0] << COUNT;
FI;





KSHIFTLW/KSHIFTLB/KSHIFTLQ/KSHIFTLD—Shift Left Mask Registers                                                                         Vol. 2A 3-523
KSHIFTLD
COUNT := imm8[7:0]
DEST[MAX_KL-1:0] := 0
IF COUNT <=31
THEN   DEST[31:0] := SRC1[31:0] << COUNT;
FI;

Intel C/C++ Compiler Intrinsic Equivalent

Compiler auto generates KSHIFTLW when needed.

Flags Affected

None.

Exceptions

SIMD Floating-Point Exceptions

None.

Other Exceptions

See Table 2-65, “TYPE K20 Exception Definition (VEX-Encoded OpMask Instructions w/o Memory Arg).” KSHIFTLW/KSHIFTLB/KSHIFTLQ/KSHIFTLD—Shift Left Mask Registers Vol. 2A 3-524