vgetmantsd

Get Mantissa Scalar Double

VGETMANTSD xmm1 {k1}, xmm2, xmm3/m64, imm8

Extracts mantissa from low double.

Details

Extracts the mantissa (significand) from the low 64-bit double-precision floating-point element of xmm3/m64 using the normalization mode in imm8, storing the result as a double in xmm1. Supports EVEX masking and rounding modes; the high 64 bits of xmm1 are preserved from xmm2.

Pseudocode Operation

float64 src_val ← xmm3[0:63]
int8 mode ← imm8
float64 mantissa ← extract_mantissa(src_val, mode)
xmm1[0:63] ← mantissa
xmm1[64:127] ← xmm2[64:127]

Example

VGETMANTSD xmm1, xmm2, xmm3/m64, 3

Encoding

Binary Layout
EVEX
+0
66
+4
0F
+5
3A
+6
27
+7
 
Format EVEX
Opcode EVEX.LLIG.66.0F3A.W1 27 /r ib
Extension AVX-512F

Operands

  • dest
    128-bit XMM SIMD register
  • src1
    128-bit XMM SIMD register
  • src2
    128-bit XMM SIMD register or Memory operand
  • src3
    8-bit signed immediate

Reference (Intel® SDM)

Instruction Forms

Opcode Instruction Op/En 64/32-bit Mode CPUID Description
EVEX.LLIG.66.0F3A.W1 27 /r ib VGETMANTSD xmm1 {k1}{z}, xmm2, xmm3/m64{sae}, imm8 A V/V AVX512F OR AVX10.1 Extract the normalized mantissa of the low float64 element in xmm3/m64 using imm8 for sign control and mantissa interval normalization. Store the mantissa to xmm1 under the writemask k1 and merge with the other elements of xmm2.

Instruction Operand Encoding

Op/En Tuple Type Operand 1 Operand 2 Operand 3 Operand 4
A Tuple1 Scalar ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) N/A

Description

Convert the double precision floating values in the low quadword element of the second source operand (the third operand) to double precision floating-point value with the mantissa normalization and sign control specified by the imm8 byte, see Figure 5-15. The converted result is written to the low quadword element of the destination operand (the first operand) using writemask k1. Bits (127:64) of the XMM register destination are copied from corresponding bits in the first source operand. The normalized mantissa is specified by interv (imm8[1:0]) and the sign control (sc) is specified by bits 3:2 of the immediate byte. The conversion operation is: GetMant(x) = ±2k|x.significand| where: 1 <= |x.significand| < 2 Unbiased exponent k can be either 0 or -1, depending on the interval range defined by interv, the range of the significand and whether the exponent of the source is even or odd. The sign of the final result is determined by sc and the source sign. The encoded value of imm8[1:0] and sign control are shown in Figure 5-15. The converted double precision floating-point result is encoded according to the sign control, the unbiased exponent k (adding bias) and a mantissa normalized to the range specified by interv. The GetMant() function follows Table 5-16 when dealing with floating-point special numbers. If writemasking is used, the low quadword element of the destination operand is conditionally updated depending on the value of writemask register k1. If writemasking is not used, the low quadword element of the destination operand is unconditionally updated. VGETMANTSD—Extract Float64 of Normalized Mantissa From Float64 Scalar Vol. 2C 5-400

Operation

// getmant_fp64(src, sign_control, normalization_interval) is defined in the operation section of VGETMANTPD

VGETMANTSD (EVEX encoded version)
SignCtrl[1:0] := IMM8[3:2];
Interv[1:0] := IMM8[1:0];
IF k1[0] OR *no writemask*
THEN DEST[63:0] :=
getmant_fp64(src, sign_control, normalization_interval)
ELSE
IF *merging-masking*                                 ; merging-masking
THEN *DEST[63:0] remains unchanged*
ELSE                                                         ; zeroing-masking
DEST[63:0] := 0
FI
FI;
DEST[127:64] := SRC1[127:64]
DEST[MAXVL-1:128] := 0

Intel C/C++ Compiler Intrinsic Equivalent

VGETMANTSD __m128d _mm_getmant_sd( __m128d a, __m128 b, enum intv, enum sgn);
VGETMANTSD __m128d _mm_mask_getmant_sd(__m128d s, __mmask8 k, __m128d a, __m128d b, enum intv, enum sgn);
VGETMANTSD __m128d _mm_maskz_getmant_sd( __mmask8 k, __m128 a, __m128d b, enum intv, enum sgn);
VGETMANTSD __m128d _mm_getmant_round_sd( __m128d a, __m128 b, enum intv, enum sgn, int r);
VGETMANTSD __m128d _mm_mask_getmant_round_sd(__m128d s, __mmask8 k, __m128d a, __m128d b, enum intv, enum sgn, int r);
VGETMANTSD __m128d _mm_maskz_getmant_round_sd( __mmask8 k, __m128d a, __m128d b, enum intv, enum sgn, int r);

Exceptions

SIMD Floating-Point Exceptions

Denormal, Invalid

Other Exceptions

See Table 2-49, “Type E3 Class Exception Conditions.” VGETMANTSD—Extract Float64 of Normalized Mantissa From Float64 Scalar Vol. 2C 5-401