serialize
Serialize Instruction Execution
SERIALIZE
Forces serialization of instruction fetch/execution.
Details
Serializes instruction execution by ensuring all prior instructions have completed and all memory operations are ordered before subsequent instructions execute. This instruction blocks out-of-order execution, flushes the pipeline, and may have significant performance impact. No flags are modified; the instruction requires SERIALIZE CPU feature and may incur substantial latency.
Pseudocode Operation
Example
SERIALIZE
Encoding
Binary Layout
0F
+0
01
+1
E8
+2
Operands
Reference (Intel® SDM)
Instruction Forms
| Opcode | Instruction | Op/En | 64/32-bit Mode | CPUID | Description |
|---|---|---|---|---|---|
| NP 0F 01 E8 | SERIALIZE | ZO | V/V | SERIALIZE | Serialize instruction fetch and execution. |
Description
Serializes instruction execution. Before the next instruction is fetched and executed, the SERIALIZE instruction ensures that all modifications to flags, registers, and memory by previous instructions are completed, draining all buffered writes to memory. This instruction is also a serializing instruction as defined in the section “Serializing
Instructions” in Chapter 11 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.
SERIALIZE does not modify registers, arithmetic flags, or memory.
Operation
Wait_On_Fetch_And_Execution_Of_Next_Instruction_Until(preceding_instructions_complete_and_preceding_stores_globally_visible);
Intel C/C++ Compiler Intrinsic Equivalent
SERIALIZE void _serialize(void);
Exceptions
SIMD Floating-Point Exceptions
None.
Other Exceptions
#UD If the LOCK prefix is used.
If CPUID.07H.00H:EDX.SERIALIZE[14] = 0.
SERIALIZE—Serialize Instruction Execution Vol. 2B 4-621