cvtpd2dq
Convert Packed Double-Precision to Packed Doubleword
Converts two doubles to two 32-bit integers (Rounded).
Pseudocode Operation
rounding_mode ← MXCSR[13:11]
dest[31:0] ← CVTI32(src[63:0], rounding_mode) // lower double to 32-bit int
dest[63:32] ← CVTI32(src[127:64], rounding_mode) // upper double to 32-bit int
dest[127:64] ← 0Encoding
Operands
-
dest
128-bit XMM SIMD register -
src
128-bit XMM SIMD register or Memory operand
Related
More in SSE2
Reference
Instruction Forms
| Opcode | Instruction | Op/En | 64/32-bit Mode | CPUID | Description |
|---|---|---|---|---|---|
| F2 0F E6 /r | CVTPD2DQ xmm1, xmm2/m128 | A | V/V | SSE2 | Convert two packed double precision floating-point values in xmm2/mem to two signed doubleword integers in xmm1. |
| VEX.128.F2.0F.WIG E6 /r | VCVTPD2DQ xmm1, xmm2/m128 | A | V/V | AVX | Convert two packed double precision floating-point values in xmm2/mem to two signed doubleword integers in xmm1. |
| VEX.256.F2.0F.WIG E6 /r | VCVTPD2DQ xmm1, ymm2/m256 | A | V/V | AVX | Convert four packed double precision floating-point values in ymm2/mem to four signed doubleword integers in xmm1. |
| EVEX.128.F2.0F.W1 E6 /r | VCVTPD2DQ xmm1 {k1}{z}, xmm2/m128/m64bcst | B | V/V | (AVX512VL AND AVX512F) OR AVX10.1 | Convert two packed double precision floating-point values in xmm2/m128/m64bcst to two signed doubleword integers in xmm1 subject to writemask k1. |
| EVEX.256.F2.0F.W1 E6 /r | VCVTPD2DQ xmm1 {k1}{z}, ymm2/m256/m64bcst | B | V/V | (AVX512VL AND AVX512F) OR AVX10.1 | Convert four packed double precision floating-point values in ymm2/m256/m64bcst to four signed doubleword integers in xmm1 subject to writemask k1. |
| EVEX.512.F2.0F.W1 E6 /r | VCVTPD2DQ ymm1 {k1}{z}, zmm2/m512/m64bcst {er} | B | V/V | AVX512F OR AVX10.1 | Convert eight packed double precision floatingpoint values in zmm2/m512/m64bcst to eight signed doubleword integers in ymm1 subject to writemask k1. |
Instruction Operand Encoding
| Op/En | Tuple Type | Operand 1 | Operand 2 | Operand 3 | Operand 4 |
|---|---|---|---|---|---|
| A | N/A | ModRM:reg (w) | ModRM:r/m (r) | N/A | N/A |
| B | Full | ModRM:reg (w) | ModRM:r/m (r) | N/A | N/A |
Description
Converts packed double precision floating-point values in the source operand (second operand) to packed signed doubleword integers in the destination operand (first operand). When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR register or the embedded rounding control bits. If a converted result cannot be represented in the destination format, the floating-point invalid exception is raised, and if this exception is masked, the indefinite integer value 80000000H is returned. EVEX encoded versions: The source operand is a ZMM/YMM/XMM register, a 512-bit memory location, or a 512-bit vector broadcasted from a 64-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally updated with writemask k1. The upper bits (MAXVL-1:256/128/64) of the corresponding destination are zeroed. VEX.256 encoded version: The source operand is a YMM register or 256- bit memory location. The destination operand is an XMM register. The upper bits (MAXVL-1:128) of the corresponding ZMM register destination are zeroed. VEX.128 encoded version: The source operand is an XMM register or 128- bit memory location. The destination operand is a XMM register. The upper bits (MAXVL-1:64) of the corresponding ZMM register destination are zeroed. 128-bit Legacy SSE version: The source operand is an XMM register or 128- bit memory location. The destination operand is an XMM register. Bits[127:64] of the destination XMM register are zeroed. However, the upper bits (MAXVL-1:128) of the corresponding ZMM register destination are unmodified.
VEX.vvvv and EVEX.vvvv are reserved and must be 1111b, otherwise instructions will #UD.
Operation
VCVTPD2DQ (EVEX Encoded Versions) When SRC Operand is a Register (KL, VL) = (2, 128), (4, 256), (8, 512) IF (VL = 512) AND (EVEX.b = 1) THEN SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(EVEX.RC); ELSE SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(MXCSR.RC); FI; FOR j := 0 TO KL-1 i := j * 32 k := j * 64 IF k1[j] OR *no writemask* THEN DEST[i+31:i] := Convert_Double_Precision_Floating_Point_To_Integer(SRC[k+63:k]) ELSE IF *merging-masking* ; merging-masking THEN *DEST[i+31:i] remains unchanged* ELSE ; zeroing-masking DEST[i+31:i] := 0 FI FI; ENDFOR DEST[MAXVL-1:VL/2] := 0 VCVTPD2DQ (EVEX Encoded Versions) When SRC Operand is a Memory Source (KL, VL) = (2, 128), (4, 256), (8, 512) FOR j := 0 TO KL-1 i := j * 32 k := j * 64 IF k1[j] OR *no writemask* THEN IF (EVEX.b = 1) THEN DEST[i+31:i] := Convert_Double_Precision_Floating_Point_To_Integer(SRC[63:0]) ELSE DEST[i+31:i] := Convert_Double_Precision_Floating_Point_To_Integer(SRC[k+63:k]) FI; ELSE IF *merging-masking* ; merging-masking THEN *DEST[i+31:i] remains unchanged* ELSE ; zeroing-masking DEST[i+31:i] := 0 FI FI; ENDFOR DEST[MAXVL-1:VL/2] := 0 VCVTPD2DQ (VEX.256 Encoded Version) DEST[31:0] := Convert_Double_Precision_Floating_Point_To_Integer(SRC[63:0]) DEST[63:32] := Convert_Double_Precision_Floating_Point_To_Integer(SRC[127:64]) DEST[95:64] := Convert_Double_Precision_Floating_Point_To_Integer(SRC[191:128]) DEST[127:96] := Convert_Double_Precision_Floating_Point_To_Integer(SRC[255:192) DEST[MAXVL-1:128] := 0 VCVTPD2DQ (VEX.128 Encoded Version) DEST[31:0] := Convert_Double_Precision_Floating_Point_To_Integer(SRC[63:0]) DEST[63:32] := Convert_Double_Precision_Floating_Point_To_Integer(SRC[127:64]) DEST[MAXVL-1:64] := 0 CVTPD2DQ (128-bit Legacy SSE Version) DEST[31:0] := Convert_Double_Precision_Floating_Point_To_Integer(SRC[63:0]) DEST[63:32] := Convert_Double_Precision_Floating_Point_To_Integer(SRC[127:64]) DEST[127:64] := 0 DEST[MAXVL-1:128] (unmodified)
Intel C/C++ Compiler Intrinsic Equivalent
VCVTPD2DQ __m256i _mm512_cvtpd_epi32( __m512d a); VCVTPD2DQ __m256i _mm512_mask_cvtpd_epi32( __m256i s, __mmask8 k, __m512d a); VCVTPD2DQ __m256i _mm512_maskz_cvtpd_epi32( __mmask8 k, __m512d a); VCVTPD2DQ __m256i _mm512_cvt_roundpd_epi32( __m512d a, int r); VCVTPD2DQ __m256i _mm512_mask_cvt_roundpd_epi32( __m256i s, __mmask8 k, __m512d a, int r); VCVTPD2DQ __m256i _mm512_maskz_cvt_roundpd_epi32( __mmask8 k, __m512d a, int r); VCVTPD2DQ __m128i _mm256_mask_cvtpd_epi32( __m128i s, __mmask8 k, __m256d a); VCVTPD2DQ __m128i _mm256_maskz_cvtpd_epi32( __mmask8 k, __m256d a); VCVTPD2DQ __m128i _mm_mask_cvtpd_epi32( __m128i s, __mmask8 k, __m128d a); VCVTPD2DQ __m128i _mm_maskz_cvtpd_epi32( __mmask8 k, __m128d a); VCVTPD2DQ __m128i _mm256_cvtpd_epi32 (__m256d src) CVTPD2DQ __m128i _mm_cvtpd_epi32 (__m128d src)