sqrtss

Square Root Scalar Single-Precision

SQRTSS xmm1, xmm2/m32

Computes square root of the low float.

Details

Computes the square root of the low 32-bit single-precision floating-point value in xmm2/m32 and stores the result in the low 32 bits of xmm1; the upper 96 bits of xmm1 are set to zero. This operation follows IEEE 754 semantics and does not modify EFLAGS; negative operands produce NaN.

Pseudocode Operation

xmm1[0:31] ← FP32_sqrt(xmm2/m32[0:31])
xmm1[32:127] ← 0

Example

SQRTSS xmm1, xmm2/m32

Encoding

Binary Layout
F3
+0
0F
+1
51
+2
 
Format SSE
Opcode F3 0F 51
Extension SSE

Operands

  • dest
    128-bit XMM SIMD register
  • src
    128-bit XMM SIMD register or Memory operand

Reference (Intel® SDM)

Instruction Forms

Opcode Instruction Op/En 64/32-bit Mode CPUID Description
F3 0F 51 /r SQRTSS xmm1, xmm2/m32 A V/V SSE Computes square root of the low single precision floatingpoint value in xmm2/m32 and stores the results in xmm1.
VEX.LIG.F3.0F.WIG 51 /r VSQRTSS xmm1, xmm2, xmm3/m32 B V/V AVX Computes square root of the low single precision floatingpoint value in xmm3/m32 and stores the results in xmm1. Also, upper single precision floating-point values (bits[127:32]) from xmm2 are copied to xmm1[127:32].
EVEX.LLIG.F3.0F.W0 51 /r VSQRTSS xmm1 {k1}{z}, xmm2, xmm3/m32{er} C V/V AVX512F OR AVX10.1 Computes square root of the low single precision floatingpoint value in xmm3/m32 and stores the results in xmm1 under writemask k1. Also, upper single precision floatingpoint values (bits[127:32]) from xmm2 are copied to xmm1[127:32].

Instruction Operand Encoding

Op/En Tuple Type Operand 1 Operand 2 Operand 3 Operand 4
A N/A ModRM:reg (w) ModRM:r/m (r) N/A N/A
B N/A ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) N/A
C Tuple1 Scalar ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) N/A

Description

Computes the square root of the low single precision floating-point value in the second source operand and stores the single precision floating-point result in the destination operand. The second source operand can be an XMM register or a 32-bit memory location. The first source and destination operands is an XMM register. 128-bit Legacy SSE version: The first source operand and the destination operand are the same. Bits (MAXVL1:32) of the corresponding YMM destination register remain unchanged. VEX.128 and EVEX encoded versions: Bits 127:32 of the destination operand are copied from the corresponding bits of the first source operand. Bits (MAXVL-1:128) of the destination ZMM register are zeroed. EVEX encoded version: The low doubleword element of the destination operand is updated according to the writemask. Software should ensure VSQRTSS is encoded with VEX.L=0. Encoding VSQRTSS with VEX.L=1 may encounter unpredictable behavior across different processor generations. SQRTSS—Compute Square Root of Scalar Single Precision Value Vol. 2B 4-668

Operation

VSQRTSS (EVEX Encoded Version)
IF (EVEX.b = 1) AND (SRC2 *is register*)
THEN
SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(EVEX.RC);
ELSE
SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(MXCSR.RC);
FI;
IF k1[0] or *no writemask*
THEN   DEST[31:0] := SQRT(SRC2[31:0])
ELSE
IF *merging-masking*                                 ; merging-masking
THEN *DEST[31:0] remains unchanged*
ELSE                                                         ; zeroing-masking
DEST[31:0] := 0
FI;
FI;
DEST[127:32] := SRC1[127:32]
DEST[MAXVL-1:128] := 0

VSQRTSS (VEX.128 Encoded Version)
DEST[31:0] := SQRT(SRC2[31:0])
DEST[127:32] := SRC1[127:32]
DEST[MAXVL-1:128] := 0

SQRTSS (128-bit Legacy SSE Version)
DEST[31:0] := SQRT(SRC2[31:0])
DEST[MAXVL-1:32] (Unmodified)

Intel C/C++ Compiler Intrinsic Equivalent

VSQRTSS __m128 _mm_sqrt_round_ss(__m128 a, __m128 b, int r);
VSQRTSS __m128 _mm_mask_sqrt_round_ss(__m128 s, __mmask8 k, __m128 a, __m128 b, int r);
VSQRTSS __m128 _mm_maskz_sqrt_round_ss( __mmask8 k, __m128 a, __m128 b, int r);
SQRTSS __m128 _mm_sqrt_ss(__m128 a)

Exceptions

SIMD Floating-Point Exceptions

Invalid, Precision, Denormal.

Other Exceptions

Non-EVEX-encoded instruction, see Table 2-20, “Type 3 Class Exception Conditions.” EVEX-encoded instruction, see Table 2-49, “Type E3 Class Exception Conditions.” SQRTSS—Compute Square Root of Scalar Single Precision Value Vol. 2B 4-669