vsha512msg2

SHA512 Message Schedule 2

VSHA512MSG2 ymm1, ymm2

SHA512 final calculation (AVX512).

Details

Computes the second stage of SHA-512 message schedule expansion, combining two 256-bit YMM inputs to produce a 256-bit result. This instruction is used after VSHA512MSG1 to complete the message schedule preparation for SHA-512 block processing. No EFLAGS are modified.

Pseudocode Operation

W[0..3] ← ymm1[64*i..64*i+63] for i in 0 to 3
W[4..7] ← ymm2[64*i..64*i+63] for i in 0 to 3
result ← sha512_msg2_schedule(W[0..3], W[4..7])
ymm1[256 bits] ← result

Example

VSHA512MSG2 ymm1, ymm2

Encoding

Binary Layout
CD
+0
 
Format EVEX
Opcode VEX.256.F2.0F38.W0 CD 11:rrr:bbb
Extension SHA512

Operands

  • dest
    256-bit YMM AVX register
  • src
    256-bit YMM AVX register

Reference (Intel® SDM)

Instruction Forms

Opcode Instruction Op/En 64/32-bit Mode CPUID Description
VEX.256.F2.0F38.W0 CD 11:rrr:bbb VSHA512MSG2 ymm1, ymm2 A V/V AVX SHA512 Performs the final calculation for the next four SHA512 message qwords using previous message qwords from ymm1 and ymm2, storing the result in ymm1.

Instruction Operand Encoding

Op/En Tuple Type Operand 1 Operand 2 Operand 3 Operand 4
A N/A ModRM:reg (r, w) ModRM:r/m (r) N/A N/A

Description

The VSHA512MSG2 instruction is one of the two SHA512 message scheduling instructions. The instruction performs the final calculation for the next four SHA512 message qwords. See https://nvlpubs.nist.gov/nistpubs/FIPS/NIST.FIPS.180-4.pdf for more information on the SHA512 standard.

Operation

define ROR64(qword, n):
count := n % 64
dest := (qword >> count) | (qword << (64-count))
return dest

define SHR64(qword, n):
return qword >> n

define s1(qword):
return ROR64(qword,19) ^ ROR64(qword, 61) ^ SHR64(qword, 6)

VSHA512MSG2 SRCDEST, SRC1
W[14] := SRC1.qword[2]
W[15] := SRC1.qword[3]
W[16] := SRCDEST.qword[0] + s1(W[14])
W[17] := SRCDEST.qword[1] + s1(W[15])
W[18] := SRCDEST.qword[2] + s1(W[16])
W[19] := SRCDEST.qword[3] + s1(W[17])

SRCDEST.qword[3] := W[19]
SRCDEST.qword[2] := W[18]
SRCDEST.qword[1] := W[17]
SRCDEST.qword[0] := W[16]

Intel C/C++ Compiler Intrinsic Equivalent

VSHA512MSG2 __m256i _mm256_sha512msg2_epi64 (__m256i __A, __m256i __B);

Flags Affected

None.

Exceptions

SIMD Floating-Point Exceptions

None. VSHA512MSG2—Perform a Final Calculation for the Next Four SHA512 Message Qwords Vol. 2C 5-746

Other Exceptions

See Table 2-23, “Type 6 Class Exception Conditions.” VSHA512MSG2—Perform a Final Calculation for the Next Four SHA512 Message Qwords Vol. 2C 5-747