minsd

Minimum Scalar Double-Precision

MINSD xmm1, xmm2/m64

Returns the minimum of two low double-precision values.

Details

Returns the minimum of the low 64-bit double-precision floating-point values from xmm1 and xmm2/m64, storing the result in xmm1; the high 64 bits of xmm1 are preserved. Comparison follows IEEE 754 rules where NaN comparisons return NaN and negative zero is less than positive zero; EFLAGS are not modified.

Pseudocode Operation

xmm1[0:63] ← FP64_min(xmm1[0:63], xmm2/m64[0:63])
xmm1[64:127] ← unchanged

Example

MINSD xmm1, xmm2/m64

Encoding

Binary Layout

Format SSE2

Opcode F2 0F 5D

Extension SSE2

Operands

dest
128-bit XMM SIMD register
src
128-bit XMM SIMD register or Memory operand

Reference (Intel® SDM)

Instruction Forms

Opcode	Instruction	Op/En	64/32-bit Mode	CPUID	Description
F2 0F 5D /r	MINSD xmm1, xmm2/m64	A	V/V	SSE2	Return the minimum scalar double precision floatingpoint value between xmm2/m64 and xmm1.
VEX.LIG.F2.0F.WIG 5D /r	VMINSD xmm1, xmm2, xmm3/m64	B	V/V	AVX	Return the minimum scalar double precision floatingpoint value between xmm3/m64 and xmm2.
EVEX.LLIG.F2.0F.W1 5D /r	VMINSD xmm1 {k1}{z}, xmm2, xmm3/m64{sae}	C	V/V	AVX512F OR AVX10.1	Return the minimum scalar double precision floatingpoint value between xmm3/m64 and xmm2.

Instruction Operand Encoding

Op/En	Tuple Type	Operand 1	Operand 2	Operand 3	Operand 4
A	N/A	ModRM:reg (r, w)	ModRM:r/m (r)	N/A	N/A
B	N/A	ModRM:reg (w)	VEX.vvvv (r)	ModRM:r/m (r)	N/A
C	Tuple1 Scalar	ModRM:reg (w)	EVEX.vvvv (r)	ModRM:r/m (r)	N/A

Description

Compares the low double precision floating-point values in the first source operand and the second source operand, and returns the minimum value to the low quadword of the destination operand. When the source operand is a memory operand, only the 64 bits are accessed. If the values being compared are both 0.0s (of either sign), the value in the second source operand is returned. If a value in the second source operand is an SNaN, then SNaN is returned unchanged to the destination (that is, a QNaN version of the SNaN is not returned). If only one value is a NaN (SNaN or QNaN) for this instruction, the second source operand, either a NaN or a valid floating-point value, is written to the result. If instead of this behavior, it is required that the NaN source operand (from either the first or second source) be returned, the action of MINSD can be emulated using a sequence of instructions, such as, a comparison followed by AND, ANDN, and OR. The second source operand can be an XMM register or a 64-bit memory location. The first source and destination operands are XMM registers. 128-bit Legacy SSE version: The destination and first source operand are the same. Bits (MAXVL-1:64) of the corresponding destination register remain unchanged. VEX.128 and EVEX encoded version: Bits (127:64) of the XMM register destination are copied from corresponding bits in the first source operand. Bits (MAXVL-1:128) of the destination register are zeroed. EVEX encoded version: The low quadword element of the destination operand is updated according to the writemask. Software should ensure VMINSD is encoded with VEX.L=0. Encoding VMINSD with VEX.L=1 may encounter unpredictable behavior across different processor generations. MINSD—Return Minimum Scalar Double Precision Floating-Point Value Vol. 2B 4-22

Operation

MIN(SRC1, SRC2)
{
IF ((SRC1 = 0.0) and (SRC2 = 0.0)) THEN DEST := SRC2;
ELSE IF (SRC1 = NaN) THEN DEST := SRC2; FI;
ELSE IF (SRC2 = NaN) THEN DEST := SRC2; FI;
ELSE IF (SRC1 < SRC2) THEN DEST := SRC1;
ELSE DEST := SRC2;
FI;
}

MINSD (EVEX Encoded Version)
IF k1[0] or *no writemask*
THEN   DEST[63:0] := MIN(SRC1[63:0], SRC2[63:0])
ELSE
IF *merging-masking*                                 ; merging-masking
THEN *DEST[63:0] remains unchanged*
ELSE                                                         ; zeroing-masking
THEN DEST[63:0] := 0
FI;
FI;
DEST[127:64] := SRC1[127:64]
DEST[MAXVL-1:128] := 0

MINSD (VEX.128 Encoded Version)
DEST[63:0] := MIN(SRC1[63:0], SRC2[63:0])
DEST[127:64] := SRC1[127:64]
DEST[MAXVL-1:128] := 0

MINSD (128-bit Legacy SSE Version)
DEST[63:0] := MIN(SRC1[63:0], SRC2[63:0])
DEST[MAXVL-1:64] (Unmodified)

Intel C/C++ Compiler Intrinsic Equivalent

VMINSD __m128d _mm_min_round_sd(__m128d a, __m128d b, int);
VMINSD __m128d _mm_mask_min_round_sd(__m128d s, __mmask8 k, __m128d a, __m128d b, int);
VMINSD __m128d _mm_maskz_min_round_sd( __mmask8 k, __m128d a, __m128d b, int);
MINSD __m128d _mm_min_sd(__m128d a, __m128d b)

Exceptions

SIMD Floating-Point Exceptions

Invalid (including QNaN Source Operand), Denormal.

Other Exceptions

Non-EVEX-encoded instruction, see Table 2-20, “Type 3 Class Exception Conditions.” EVEX-encoded instruction, see Table 2-49, “Type E3 Class Exception Conditions.” MINSD—Return Minimum Scalar Double Precision Floating-Point Value Vol. 2B 4-23