movntsd

Move Non-Temporal Scalar Double

MOVNTSD m64, xmm1

Stores scalar double bypassing cache (AMD SSE4a).

Pseudocode Operation

[dest] ← src[63:0];

Example

MOVNTSD [rbp-8], xmm1

Encoding

Binary Layout

F2

+0

0F

+1

2B

+2

 

Format SSE4a

Opcode F2 0F 2B /r

Extension SSE4a

Operands

• dest
  64-bit memory operand (quadword)
• src
  128-bit XMM SIMD register

Related

More in SSE4a

Reference

View in Intel® 64 and IA-32 Architectures SDM ↗ AMD APM

Instruction Forms

Opcode	Instruction	Op/En	64/32-bit Mode	CPUID	Description
F2 0F 2B /r	MOVNTSD m64, xmm1				Non-temporal store of the low scalar double-precision value in xmm1 to m64.

Description

Double-Precision Floating-Point Stores one double-precision floating-point value from an XMM register to a 64-bit memory location. This instruction indicates to the processor that the data is non-temporal, and is unlikely to be used again soon. The processor treats the store as a write-combining memory write, which minimizes cache pollution. The diagram below illustrates the operation of this instruction: mem64 XMM register

63 0 127 64 63 0 copy

Flags Affected

None 218 [AMDMOVNTSDPublic Use] Instruction Reference