fucom

Unordered Compare Real

FUCOM ST(i)

Compares ST(0) with source (supports NaNs).

Details

Compares the top of the x87 FPU stack (ST(0)) with an operand (ST(i) by default) and sets condition code bits in the FPU status word. Unlike FCOM, FUCOM treats QNaN operands as comparable rather than signaling. The C3, C2, and C0 bits are set based on the comparison result (unordered, greater than, less than, or equal), and C1 is cleared.

Pseudocode Operation

if (is_unordered(ST(0), ST(i))) {
  C3 ← 1; C2 ← 1; C0 ← 1
} else if (ST(0) > ST(i)) {
  C3 ← 0; C2 ← 0; C0 ← 0
} else if (ST(0) < ST(i)) {
  C3 ← 0; C2 ← 0; C0 ← 1
} else {
  C3 ← 1; C2 ← 0; C0 ← 0
}
C1 ← 0

Example

FUCOM st(1)

Encoding

Binary Layout
DD
+0
 
Format Legacy
Opcode DD E0+i
Extension x87 FPU

Operands

  • src
    Reg

Reference (Intel® SDM)

Instruction Forms

Opcode Instruction Op/En 64/32-bit Mode CPUID Description
DD E0+i FUCOM ST(i) Valid Valid Compare ST(0) with ST(i).
DD E1 FUCOM Valid Valid Compare ST(0) with ST(1).
DD E8+i FUCOMP ST(i) Valid Valid Compare ST(0) with ST(i) and pop register stack.
DD E9 FUCOMP Valid Valid Compare ST(0) with ST(1) and pop register stack.
DA E9 FUCOMPP Valid Valid Compare ST(0) with ST(1) and pop register stack twice.

Description

Performs an unordered comparison of the contents of register ST(0) and ST(i) and sets condition code flags C0, C2, and C3 in the FPU status word according to the results (see the table below). If no operand is specified, the contents of registers ST(0) and ST(1) are compared. The sign of zero is ignored, so that –0.0 is equal to +0.0. Table 3-43. FUCOM/FUCOMP/FUCOMPP Results Comparison Results* C3 C2 C0 ST0 > ST(i) 0 0 0 ST0 < ST(i) 0 0 1 ST0 = ST(i) 1 0 0 Unordered 1 1 1

Operation

CASE (relation of operands) OF
ST > SRC:         C3, C2, C0 := 000;
ST < SRC:         C3, C2, C0 := 001;
ST = SRC:         C3, C2, C0 := 100;
ESAC;
IF ST(0) or SRC = QNaN, but not SNaN or unsupported format
THEN
C3, C2, C0 := 111;
ELSE (* ST(0) or SRC is SNaN or unsupported format *)
#IA;
IF FPUControlWord.IM = 1
THEN
C3, C2, C0 := 111;
FI;
FI;
IF Instruction = FUCOMP
THEN
PopRegisterStack;
FI;
IF Instruction = FUCOMPP
THEN
PopRegisterStack;
FI;

Exceptions

Protected Mode Exceptions

#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. #MF If there is a pending x87 FPU exception. #UD If the LOCK prefix is used.

Real-Address Mode Exceptions

Same exceptions as in protected mode.

Virtual-8086 Mode Exceptions

Same exceptions as in protected mode.

Compatibility Mode Exceptions

Same exceptions as in protected mode.

64-Bit Mode Exceptions

Same exceptions as in protected mode. FUCOM/FUCOMP/FUCOMPP—Unordered Compare Floating-Point Values Vol. 2A 3-403 FUCOM/FUCOMP/FUCOMPP—Unordered Compare Floating-Point Values Vol. 2A 3-404