comisd

Compare Scalar Ordered Double-Precision

COMISD xmm1, xmm2/m64

Compares low double and sets EFLAGS (Signaling NaN raises exception).

Details

Performs an ordered comparison of the low double-precision floating-point values in two XMM registers or memory, setting EFLAGS (ZF, PF, CF) accordingly. Signals invalid operation exception if either operand is a signaling NaN; quiet NaNs set ZF=1, PF=1, CF=1. Does not modify the XMM registers.

Pseudocode Operation

src1_val ← src1[0:63] (as double); src2_val ← src2[0:63] (as double); if (IsNaN(src1_val) || IsNaN(src2_val)) { ZF ← 1; PF ← 1; CF ← 1; OF ← 0; AF ← 0; SF ← 0; } else if (src1_val < src2_val) { CF ← 1; ZF ← 0; PF ← 0; OF ← 0; AF ← 0; SF ← 0; } else if (src1_val == src2_val) { ZF ← 1; CF ← 0; PF ← 0; OF ← 0; AF ← 0; SF ← 0; } else { ZF ← 0; CF ← 0; PF ← 0; OF ← 0; AF ← 0; SF ← 0; }

Example

COMISD xmm1, xmm2/m64

Encoding

Binary Layout

Format SSE2

Opcode 66 0F 2F

Extension SSE2

Operands

src1
XMM
src2
XMM/Mem

Reference (Intel® SDM)

Instruction Forms

Opcode	Instruction	Op/En	64/32-bit Mode	CPUID	Description
66 0F 2F /r	COMISD xmm1, xmm2/m64	A	V/V	SSE2	Compare low double precision floating-point values in xmm1 and xmm2/mem64 and set the EFLAGS flags accordingly.
VEX.LIG.66.0F.WIG 2F /r	VCOMISD xmm1, xmm2/m64	A	V/V	AVX	Compare low double precision floating-point values in xmm1 and xmm2/mem64 and set the EFLAGS flags accordingly.
EVEX.LLIG.66.0F.W1 2F /r	VCOMISD xmm1, xmm2/m64{sae}	B	V/V	AVX512F OR AVX10.1	Compare low double precision floating-point values in xmm1 and xmm2/mem64 and set the EFLAGS flags accordingly.

Instruction Operand Encoding

Op/En	Tuple Type	Operand 1	Operand 2	Operand 3	Operand 4
A	N/A	ModRM:reg (w)	ModRM:r/m (r)	N/A	N/A
B	Tuple1 Scalar	ModRM:reg (w)	ModRM:r/m (r)	N/A	N/A

Description

Compares the double precision floating-point values in the low quadwords of operand 1 (first operand) and operand 2 (second operand), and sets the ZF, PF, and CF flags in the EFLAGS register according to the result (unordered, greater than, less than, or equal). The OF, SF, and AF flags in the EFLAGS register are set to 0. The unordered result is returned if either source operand is a NaN (QNaN or SNaN). Operand 1 is an XMM register; operand 2 can be an XMM register or a 64 bit memory location. The COMISD instruction differs from the UCOMISD instruction in that it signals a SIMD floating-point invalid operation exception (#I) when a source operand is either a QNaN or SNaN. The UCOMISD instruction signals an invalid operation exception only if a source operand is an SNaN. The EFLAGS register is not updated if an unmasked SIMD floating-point exception is generated. VEX.vvvv and EVEX.vvvv are reserved and must be 1111b, otherwise instructions will #UD. Software should ensure VCOMISD is encoded with VEX.L=0. Encoding VCOMISD with VEX.L=1 may encounter unpredictable behavior across different processor generations.

Operation

COMISD (All Versions)
RESULT :=OrderedCompare(DEST[63:0] <> SRC[63:0]) {
(* Set EFLAGS *) CASE (RESULT) OF
UNORDERED: ZF,PF,CF := 111;
GREATER_THAN: ZF,PF,CF := 000;
LESS_THAN: ZF,PF,CF := 001;
EQUAL: ZF,PF,CF := 100;
ESAC;
OF, AF, SF := 0; }





COMISD—Compare Scalar Ordered Double Precision Floating-Point Values and Set EFLAGS                                                    Vol. 2A 3-199

Intel C/C++ Compiler Intrinsic Equivalent

VCOMISD int _mm_comi_round_sd(__m128d a, __m128d b, int imm, int sae);
VCOMISD int _mm_comieq_sd (__m128d a, __m128d b)
VCOMISD int _mm_comilt_sd (__m128d a, __m128d b)
VCOMISD int _mm_comile_sd (__m128d a, __m128d b)
VCOMISD int _mm_comigt_sd (__m128d a, __m128d b)
VCOMISD int _mm_comige_sd (__m128d a, __m128d b)
VCOMISD int _mm_comineq_sd (__m128d a, __m128d b)

Exceptions

SIMD Floating-Point Exceptions

Invalid (if SNaN or QNaN operands), Denormal.

Other Exceptions

VEX-encoded instructions, see Table 2-20, “Type 3 Class Exception Conditions.” EVEX-encoded instructions, see Table 2-50, “Type E3NF Class Exception Conditions.” Additionally: #UD If VEX.vvvv != 1111B or EVEX.vvvv != 1111B. COMISD—Compare Scalar Ordered Double Precision Floating-Point Values and Set EFLAGS Vol. 2A 3-200