hsubps
Horizontal Subtract Packed Single-Precision
Subtracts adjacent single-precision elements horizontally.
Pseudocode Operation
dest[31:0] ← dest[31:0] - dest[63:32];
dest[63:32] ← dest[95:64] - dest[127:96];
dest[95:64] ← src[31:0] - src[63:32];
dest[127:96] ← src[95:64] - src[127:96];Encoding
Operands
-
dest
128-bit XMM SIMD register -
src
128-bit XMM SIMD register or Memory operand
Related
More in SSE3
Reference
Instruction Forms
| Opcode | Instruction | Op/En | 64/32-bit Mode | CPUID | Description |
|---|---|---|---|---|---|
| F2 0F 7D /r | HSUBPS xmm1, xmm2/m128 | RM | V/V | SSE3 | Horizontal subtract packed single precision floating-point values from xmm2/m128 to xmm1. |
| VEX.128.F2.0F.WIG 7D /r | VHSUBPS xmm1, xmm2, xmm3/m128 | AVX | RVM V/V Horizontal subtract packed single precision floating-point values from xmm2 and xmm3/mem. | ||
| VEX.256.F2.0F.WIG 7D /r | VHSUBPS ymm1, ymm2, ymm3/m256 | AVX | RVM V/V Horizontal subtract packed single precision floating-point values from ymm2 and ymm3/mem. |
Description
Subtracts the single precision floating-point value in the second dword of the destination operand from the first dword of the destination operand and stores the result in the first dword of the destination operand. Subtracts the single precision floating-point value in the fourth dword of the destination operand from the third dword of the destination operand and stores the result in the second dword of the destination operand. Subtracts the single precision floating-point value in the second dword of the source operand from the first dword of the source operand and stores the result in the third dword of the destination operand. Subtracts the single precision floating-point value in the fourth dword of the source operand from the third dword of the source operand and stores the result in the fourth dword of the destination operand. In 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15). See Figure 3-18 for HSUBPS; see Figure 3-19 for VHSUBPS.
HSUBPS xmm1, xmm2/m128
xmm2/
[127:96] [95:64] [63:32] [31:0] m128
[127:96] [95:64] [63:32] [31:0] xmm1
xmm2/m128 xmm2/m128 xmm1[95:64] - xmm1[31:0] - RESULT: [95:64] - xmm2/ [31:0] - xmm2/ xmm1[127:96] xmm1[63:32] xmm1 m128[127:96] m128[63:32]
[127:96] [95:64] [63:32] [31:0]
OM15996
SRC1 X7 X6 X5 X4 X3 X2 X1 X0
SRC2 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0
DEST Y6-Y7 Y4-Y5 X6-X7 X4-X5 Y2-Y3 Y0-Y1 X2-X3 X0-X1
128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The destination is not distinct from the first source XMM register and the upper bits (MAXVL-1:128) of the corresponding YMM register destination are unmodified. VEX.128 encoded version: the first source operand is an XMM register or 128-bit memory location. The destination operand is an XMM register. The upper bits (MAXVL-1:128) of the corresponding YMM register destination are zeroed. VEX.256 encoded version: The first source operand is a YMM register. The second source operand can be a YMM register or a 256-bit memory location. The destination operand is a YMM register.
Operation
HSUBPS (128-bit Legacy SSE Version) DEST[31:0] := SRC1[31:0] - SRC1[63:32] DEST[63:32] := SRC1[95:64] - SRC1[127:96] DEST[95:64] := SRC2[31:0] - SRC2[63:32] DEST[127:96] := SRC2[95:64] - SRC2[127:96] DEST[MAXVL-1:128] (Unmodified) VHSUBPS (VEX.128 Encoded Version) DEST[31:0] := SRC1[31:0] - SRC1[63:32] DEST[63:32] := SRC1[95:64] - SRC1[127:96] DEST[95:64] := SRC2[31:0] - SRC2[63:32] DEST[127:96] := SRC2[95:64] - SRC2[127:96] DEST[MAXVL-1:128] := 0 VHSUBPS (VEX.256 Encoded Version) DEST[31:0] := SRC1[31:0] - SRC1[63:32] DEST[63:32] := SRC1[95:64] - SRC1[127:96] DEST[95:64] := SRC2[31:0] - SRC2[63:32] DEST[127:96] := SRC2[95:64] - SRC2[127:96] DEST[159:128] := SRC1[159:128] - SRC1[191:160] DEST[191:160] := SRC1[223:192] - SRC1[255:224] DEST[223:192] := SRC2[159:128] - SRC2[191:160] DEST[255:224] := SRC2[223:192] - SRC2[255:224]
Intel C/C++ Compiler Intrinsic Equivalent
HSUBPS __m128 _mm_hsub_ps(__m128 a, __m128 b); VHSUBPS __m256 _mm256_hsub_ps (__m256 a, __m256 b);