sha1msg1

SHA1 Message Schedule 1

SHA1MSG1 xmm1, xmm2/m128

Performs intermediate calculation for SHA1 message schedule.

Details

Performs the first intermediate step of SHA-1 message schedule expansion on 128-bit XMM operands, computing partial W values (message words) for rounds 16–19. The destination is updated with results of the schedule computation; no flags are affected.

Pseudocode Operation

W[0..3] ← dest[0..3];
W[4..7] ← src[0..3];
for i in 0..3:
  dest[i] ← W[i] ⊕ W[i+2] ⊕ W[i+8] ⊕ W[i+13];

Example

SHA1MSG1 xmm1, xmm2/m128

Encoding

Binary Layout
0F
+0
38
+1
C9
+2
 
Format Legacy
Opcode NP 0F 38 C9 /r
Extension SHA

Operands

  • dest
    128-bit XMM SIMD register
  • src
    128-bit XMM SIMD register or Memory operand

Reference (Intel® SDM)

Instruction Forms

Opcode Instruction Op/En 64/32-bit Mode CPUID Description
NP 0F 38 C9 /r SHA1MSG1 xmm1, xmm2/m128 RM V/V SHA Performs an intermediate calculation for the next four SHA1 message dwords using previous message dwords from xmm1 and xmm2/m128, storing the result in xmm1.

Description

The SHA1MSG1 instruction is one of two SHA1 message scheduling instructions. The instruction performs an intermediate calculation for the next four SHA1 message dwords.

Operation

SHA1MSG1
W0 := SRC1[127:96] ;
W1 := SRC1[95:64] ;
W2 := SRC1[63: 32] ;
W3 := SRC1[31: 0] ;
W4 := SRC2[127:96] ;
W5 := SRC2[95:64] ;

DEST[127:96] := W2 XOR W0;
DEST[95:64] := W3 XOR W1;
DEST[63:32] := W4 XOR W2;
DEST[31:0] := W5 XOR W3;

Intel C/C++ Compiler Intrinsic Equivalent

SHA1MSG1 __m128i _mm_sha1msg1_epu32(__m128i, __m128i);

Flags Affected

None.

Exceptions

SIMD Floating-Point Exceptions

None.

Other Exceptions

See Table 2-21, “Type 4 Class Exception Conditions.” SHA1MSG1—Perform an Intermediate Calculation for the Next Four SHA1 Message Dwords Vol. 2B 4-630