t1mskc

Inverse Mask From Trailing Ones

T1MSKC r32, r/m32

Creates mask from trailing ones (~x | (x+1)).

Details

Creates a mask from trailing ones by computing ~src | (src + 1), isolating all bits from the least significant one through trailing ones. This TBM instruction operates on 32-bit operands and does not modify CPU flags.

Pseudocode Operation

dest ← ~src | (src + 1)

Example

T1MSKC eax, ebx

Encoding

Binary Layout
VEX
+0
opcode
+3
ModRM
+4
 
Format TBM
Opcode XOP.L0.09.W0 01 /7
Extension TBM

Operands

  • dest
    32-bit general-purpose register (e.g. EAX)
  • src
    32-bit register or memory

Reference (AMD APM)

Instruction Forms

Opcode Instruction Op/En 64/32-bit Mode CPUID Description
8F RXB.09 0.dest.0.00 01 /7 T1MSKC reg32, reg/mem32
8F RXB.09 1.dest.0.00 01 /7 T1MSKC reg64, reg/mem64

Description

Finds the least significant zero bit in the source operand, clears all bits below that bit to 0, sets all other bits to 1 (including the found bit) and writes the result to the destination. If the least significant bit of the source operand is 0, the destination is written with all ones. This instruction has two operands: T1MSKC dest, src In 64-bit mode, the operand size is determined by the value of XOP.W. If XOP.W is 1, the operand size is 64-bit; if XOP.W is 0, the operand size is 32-bit. In 32-bit mode, XOP.W is ignored. 16-bit operands are not supported. The destination (dest) is a general purpose register. The source operand (src) is a general purpose register or a memory operand. The T1MSKC instruction effectively performs a bit-wise logical or of the inverse of the source operand and the result of incrementing the source operand by 1 and stores the result to the destination register: add tmp1, src, 1 not tmp2, src or dest, tmp1, tmp2 The value of the carry flag of rFLAGs is generated by the add pseudo-instruction and the remaining arithmetic flags are generated by the or pseudo-instruction. The T1MSKC instruction is a TBM instruction. Support for this instruction is indicated by CPUID Fn8000_0001_ECX[TBM] = 1. For more information on using the CPUID instruction, see the instruction reference page for the CPUID instruction on page 165. For a description of all feature flags related to instruction subset support, see Appendix D, “Instruction Subsets and CPUID Feature Flags,” on page 593.