xchg

Exchange Register/Memory with Register

XCHG r/m, r

Exchanges content of two operands.

Pseudocode Operation

temp ← dest; dest ← src; src ← temp;

Example

XCHG rbx, rax

Encoding

Binary Layout

Format Legacy

Opcode 87

Extension Base

Operands

dest
Register or memory operand
src
General-purpose register

Reference

View in Intel® 64 and IA-32 Architectures SDM ↗ Intel® SDM

Instruction Forms

Opcode	Instruction	Op/En	64/32-bit Mode	Description
90+rw	XCHG AX, r16	O	Valid Valid	Exchange r16 with AX.
90+rw	XCHG r16, AX	O	Valid Valid	Exchange AX with r16.
90+rd	XCHG EAX, r32	O	Valid Valid	Exchange r32 with EAX.
REX.W + 90+rd	XCHG RAX, r64	O	Valid N.E.	Exchange r64 with RAX.
90+rd	XCHG r32, EAX	O	Valid Valid	Exchange EAX with r32.
REX.W + 90+rd	XCHG r64, RAX	O	Valid N.E.	Exchange RAX with r64.
86 /r	XCHG r/m8, r8	MR	Valid Valid	Exchange r8 (byte register) with byte from r/m8.
86 /r	XCHG r8, r/m8	RM	Valid Valid	Exchange byte from r/m8 with r8 (byte register).
87 /r	XCHG r/m16, r16	MR	Valid Valid	Exchange r16 with word from r/m16.
87 /r	XCHG r16, r/m16	RM	Valid Valid	Exchange word from r/m16 with r16.
87 /r	XCHG r/m32, r32	MR	Valid Valid	Exchange r32 with doubleword from r/m32.
REX.W + 87 /r	XCHG r/m64, r64	MR	Valid N.E.	Exchange r64 with quadword from r/m64.
87 /r	XCHG r32, r/m32	RM	Valid Valid	Exchange doubleword from r/m32 with r32.
REX.W + 87 /r	XCHG r64, r/m64	RM	Valid N.E.	Exchange quadword from r/m64 with r64.

Description

Exchanges the contents of the destination (first) and source (second) operands. The operands can be two generalpurpose registers or a register and a memory location. If a memory operand is referenced, the processor’s locking protocol is automatically implemented for the duration of the exchange operation, regardless of the presence or absence of the LOCK prefix or of the value of the IOPL. (See the LOCK prefix description in this chapter for more information on the locking protocol.) This instruction is useful for implementing semaphores or similar data structures for process synchronization. (See “Bus Locking” in Chapter 9 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A, for more information on bus locking.) The XCHG instruction can also be used instead of the BSWAP instruction for 16-bit operands. In 64-bit mode, the instruction’s default operation size is 32 bits. Using a REX prefix in the form of REX.R permits access to additional registers (R8-R15). Using a REX prefix in the form of REX.W promotes operation to 64 bits. See the summary chart at the beginning of this section for encoding data and limits.

NOTE XCHG (E)AX, (E)AX (encoded instruction byte is 90H) is an alias for NOP regardless of data size prefixes, including REX.W.

Operation

TEMP := DEST;
DEST := SRC;
SRC := TEMP;

Flags Affected

None.

Exceptions

Protected Mode Exceptions

#GP(0) If either operand is in a non-writable segment. If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register contains a NULL segment selector. #SS(0) If a memory operand effective address is outside the SS segment limit. #PF(fault-code) If a page fault occurs. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. #UD If the LOCK prefix is used but the destination is not a memory operand.

Real-Address Mode Exceptions

#GP If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. #SS If a memory operand effective address is outside the SS segment limit. #UD If the LOCK prefix is used but the destination is not a memory operand.

Virtual-8086 Mode Exceptions

#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. #SS(0) If a memory operand effective address is outside the SS segment limit. #PF(fault-code) If a page fault occurs. #AC(0) If alignment checking is enabled and an unaligned memory reference is made. #UD If the LOCK prefix is used but the destination is not a memory operand.

Compatibility Mode Exceptions

Same exceptions as in protected mode.

64-Bit Mode Exceptions

#SS(0) If a memory address referencing the SS segment is in a non-canonical form. #GP(0) If the memory address is in a non-canonical form. #PF(fault-code) If a page fault occurs. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. #UD If the LOCK prefix is used but the destination is not a memory operand. XCHG-Exchange Register/Memory With Register Vol. 2D 6-32