vpmacssww
Vector Packed Multiply Accumulate Signed Saturate Word
Multiply-accumulate signed words with saturation.
Pseudocode Operation
for i = 0 to 7:
product ← sign_extend_32(src1[i*16:(i*16)+15]) *
sign_extend_32(src2[i*16:(i*16)+15])
sum ← product + sign_extend_32(src3[i*16:(i*16)+15])
result[i*32:(i*32)+31] ← saturate_signed_32(sum)
dest ← resultEncoding
Operands
-
dest
128-bit XMM SIMD register -
src1
128-bit XMM SIMD register -
src2
128-bit XMM SIMD register -
src3
128-bit XMM SIMD register
Related
More in XOP
Reference
Instruction Forms
| Opcode | Instruction | Op/En | 64/32-bit Mode | CPUID | Description |
|---|---|---|---|---|---|
| 8F RXB.08 0.src1.0.00 85 /r ib | VPMACSSWW xmm1, xmm2, xmm3/mem128, xmm4 |
Description
Signed Word to Signed Word Multiplies each packed 16-bit signed integer value of the first source by the corresponding packed 16bit signed integer value of the second source, then adds the corresponding packed 16-bit signed integer value of the third source to the 32-bit signed integer products. Writes eight saturated sums to the destination. Out of range results of the addition are saturated to fit into a signed 16-bit integer. For each packed value of the destination, when the value is larger than the largest signed 16-bit integer, it is saturated to 7FFFh, and when the value is smaller than the smallest signed 16-bit integer, it is saturated to 8000h. There are four operands:
VPMACSSWW dest, src1, src2, src3 dest = src1* src2 + src3
The destination is an XMM register specified by ModRM.reg. When the destination is written, bits [255:128] of the corresponding YMM register are cleared. The first source (src1) is an XMM register specified by XOP.vvvv; the second source (src2) is either an XMM register or a 128-bit memory location specified by the ModRM.r/m field; and the third source (src3) is an XMM register specified by bits [7:4] of an immediate byte. When src3 and dest designate the same XMM register, this register behaves as an accumulator.