vsha512msg1

SHA512 Message Schedule 1

VSHA512MSG1 ymm1, xmm2

SHA512 intermediate calculation (AVX512).

Details

Computes SHA-512 message schedule expansion for the first message schedule instruction, operating on a 128-bit XMM source and producing a 256-bit YMM result. This instruction is part of the SHA-512 cryptographic hash computation pipeline and requires AVX-512 or SHA512 extension support. No EFLAGS are modified.

Pseudocode Operation

W[0..3] ← xmm2[64*i..64*i+63] for i in 0 to 1
W[4..7] ← expand_sha512_msg_schedule(W[0..3])
ymm1[256 bits] ← W[4..7]

Example

VSHA512MSG1 ymm1, xmm2

Encoding

Binary Layout
CC
+0
 
Format EVEX
Opcode VEX.256.F2.0F38.W0 CC 11:rrr:bbb
Extension SHA512

Operands

  • dest
    256-bit YMM AVX register
  • src
    128-bit XMM SIMD register

Reference (Intel® SDM)

Instruction Forms

Opcode Instruction Op/En 64/32-bit Mode CPUID Description
VEX.256.F2.0F38.W0 CC 11:rrr:bbb VSHA512MSG1 ymm1, xmm2 A V/V AVX SHA512 Performs an intermediate calculation for the next four SHA512 message qwords using previous message qwords from ymm1 and xmm2, storing the result in ymm1.

Instruction Operand Encoding

Op/En Tuple Type Operand 1 Operand 2 Operand 3 Operand 4
A N/A ModRM:reg (r, w) ModRM:r/m (r) N/A N/A

Description

The VSHA512MSG1 instruction is one of the two SHA512 message scheduling instructions. The instruction performs an intermediate calculation for the next four SHA512 message qwords. See https://nvlpubs.nist.gov/nistpubs/FIPS/NIST.FIPS.180-4.pdf for more information on the SHA512 standard.

Operation

define ROR64(qword, n):
count := n % 64
dest := (qword >> count) | (qword << (64-count))
return dest

define SHR64(qword, n):
return qword >> n

define s0(qword):
return ROR64(qword,1) ^ ROR64(qword, 8) ^ SHR64(qword, 7)

VSHA512MSG1 SRCDEST, SRC1
W[4] := SRC1.qword[0]
W[3] := SRCDEST.qword[3]
W[2] := SRCDEST.qword[2]
W[1] := SRCDEST.qword[1]
W[0] := SRCDEST.qword[0]

SRCDEST.qword[3] := W[3] + s0(W[4])
SRCDEST.qword[2] := W[2] + s0(W[3])
SRCDEST.qword[1] := W[1] + s0(W[2])
SRCDEST.qword[0] := W[0] + s0(W[1])

Intel C/C++ Compiler Intrinsic Equivalent

VSHA512MSG1 __m256i _mm256_sha512msg1_epi64 (__m256i __A, __m128i __B);

Flags Affected

None.

Exceptions

SIMD Floating-Point Exceptions

None. VSHA512MSG1—Perform an Intermediate Calculation for the Next Four SHA512 Message Qwords Vol. 2C 5-744

Other Exceptions

See Table 2-23, “Type 6 Class Exception Conditions.” VSHA512MSG1—Perform an Intermediate Calculation for the Next Four SHA512 Message Qwords Vol. 2C 5-745