vphadddq

Vector Packed Horizontal Add Doubleword to Quadword

VPHADDDQ xmm1, xmm2/m128

Adds adjacent doublewords to quadwords.

Details

Adds pairs of adjacent 32-bit signed integers and stores the 64-bit sums in the destination XMM register. This is a horizontal operation that processes two 32-bit elements from each 64-bit lane, producing one 64-bit result per lane. No flags are affected.

Pseudocode Operation

for i = 0 to 1:
  result[i*64:(i*64)+63] ← sign_extend_64(src[(i*2)*32:(i*2)*32+31]) +
                            sign_extend_64(src[(i*2+1)*32:(i*2+1)*32+31])
dest ← result

Example

VPHADDDQ xmm1, xmm2/m128

Encoding

Binary Layout
VEX
+0
opcode
+3
ModRM
+4
 
Format XOP
Opcode XOP.128.09.W0 CB /r
Extension XOP

Operands

  • dest
    128-bit XMM SIMD register
  • src
    128-bit XMM SIMD register or Memory operand

Reference (AMD APM)

Instruction Forms

Opcode Instruction Op/En 64/32-bit Mode CPUID Description
8F RXB.09 0.1111.0.00 CB /r VPHADDDQ xmm1, xmm2/mem128

Description

Signed Doubleword to Signed Quadword Adds each adjacent pair of signed doubleword integer values of the source and packs the signextended sums into the corresponding quadword of the destination. There are two operands: VPHADDDQ dest, src The source is either an XMM register or a 128-bit memory location and the destination is an XMM register. Bits [255:128] of the corresponding YMM register are cleared.

Flags Affected

None None

Exceptions

Exceptions

Mode Exception Cause of Exception Real Virt Prot X Instruction not supported, as indicated by CPUID feature identifier. X X XOP instructions are only recognized in protected mode. X CR4.OSXSAVE = 0, indicated by CPUID Fn0000_0001_ECX[OSXSAVE]. X XFEATURE_ENABLED_MASK[2:1] ! = 11b. Invalid opcode, #UD X XOP.W = 1. A XOP.vvvv ! = 1111b. X XOP.L = 1. X REX, F2, F3, or 66 prefix preceding XOP prefix. X Lock prefix (F0h) preceding opcode. Device not available, #NM X CR0.TS = 1. Stack, #SS X Memory address exceeding stack segment limit or non-canonical. X Memory address exceeding data segment limit or non-canonical. General protection, #GP X Null data segment used to reference memory. Page fault, #PF X Instruction execution caused a page fault. Alignment check, #AC X Memory operand not 16-byte aligned when alignment checking enabled. X — XOP exception 768 [AMDVPHADDDQPublic Use] Instruction Reference