fdiv
Divide Floating Point
FDIV m32fp/m64fp
Divides dest by src.
Details
Divides ST(0) by the floating-point operand in memory (m32fp or m64fp) and stores the result in ST(0). The operation follows IEEE 754 semantics with the current rounding mode. The x87 FPU status flags (C0, C1, C2, C3) are updated; division-by-zero, invalid operation, underflow, overflow, or precision exceptions may be raised.
Pseudocode Operation
src_value ← load_from_memory(src);
ST(0) ← ST(0) ÷ src_value;
update_x87_status_flags();Example
FDIV m32fp/m64fp
Encoding
Binary Layout
D8
+0
ModRM
+1
Operands
-
src
Memory/Reg
Reference (Intel® SDM)
Instruction Forms
| Opcode | Instruction | Op/En | 64/32-bit Mode | CPUID | Description |
|---|---|---|---|---|---|
| D8 /6 | FDIV m32fp | Valid Valid | Divide ST(0) by m32fp and store result in ST(0). | ||
| DC /6 | FDIV m64fp | Valid Valid | Divide ST(0) by m64fp and store result in ST(0). | ||
| D8 F0+i | FDIV ST(0), ST(i) | Valid Valid | Divide ST(0) by ST(i) and store result in ST(0). | ||
| DC F8+i | FDIV ST(i), ST(0) | Valid Valid | Divide ST(i) by ST(0) and store result in ST(i). | ||
| DE F8+i | FDIVP ST(i), ST(0) | Valid Valid | Divide ST(i) by ST(0), store result in ST(i), and pop the register stack. | ||
| DE F9 | FDIVP | Valid Valid | Divide ST(1) by ST(0), store result in ST(1), and pop the register stack. | ||
| DA /6 | FIDIV m32int | Valid Valid | Divide ST(0) by m32int and store result in ST(0). | ||
| DE /6 | FIDIV m16int | Valid Valid | Divide ST(0) by m16int and store result in ST(0). |
Description
Divides the destination operand by the source operand and stores the result in the destination location. The destination operand (dividend) is always in an FPU register; the source operand (divisor) can be a register or a memory location. Source operands in memory can be in single precision or double precision floating-point format, word or doubleword integer format.
The no-operand version of the instruction divides the contents of the ST(1) register by the contents of the ST(0) register. The one-operand version divides the contents of the ST(0) register by the contents of a memory location (either a floating-point or an integer value). The two-operand version, divides the contents of the ST(0) register by the contents of the ST(i) register or vice versa.
The FDIVP instructions perform the additional operation of popping the FPU register stack after storing the result.
To pop the register stack, the processor marks the ST(0) register as empty and increments the stack pointer (TOP) by 1. The no-operand version of the floating-point divide instructions always results in the register stack being popped. In some assemblers, the mnemonic for this instruction is FDIV rather than FDIVP.
The FIDIV instructions convert an integer source operand to double extended-precision floating-point format before performing the division. When the source operand is an integer 0, it is treated as a +0.
If an unmasked divide-by-zero exception (#Z) is generated, no result is stored; if the exception is masked, an ∞ of the appropriate sign is stored in the destination operand.
The following table shows the results obtained when dividing various classes of numbers, assuming that neither overflow nor underflow occurs.
FDIV/FDIVP/FIDIV—Divide Vol. 2A 3-333
Table 3-26. FDIV/FDIVP/FIDIV Results
DEST
− ∞ − F − 0 + 0 + F + ∞ NaN
− ∞ * + 0 + 0 − 0 − 0 * NaN
− F + ∞ + F + 0 − 0 − F − ∞ NaN
− I + ∞ + F + 0 − 0 − F − ∞ NaN
SRC − 0 + ∞ ** * * ** − ∞ NaN
+ 0 − ∞ ** * * ** + ∞ NaN
+ I − ∞ − F − 0 + 0 + F + ∞ NaN
+ F − ∞ − F − 0 + 0 + F + ∞ NaN
+ ∞ * − 0 − 0 + 0 + 0 * NaN
NaN NaN NaN NaN NaN NaN NaN NaN
Operation
IF SRC = 0 THEN #Z; ELSE IF Instruction is FIDIV THEN DEST := DEST / ConvertToDoubleExtendedPrecisionFP(SRC); ELSE (* Source operand is floating-point value *) DEST := DEST / SRC; FI; FI; IF Instruction = FDIVP THEN PopRegisterStack; FI;
Exceptions
Protected Mode Exceptions
#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
If the DS, ES, FS, or GS register contains a NULL segment selector.
#SS(0) If a memory operand effective address is outside the SS segment limit.
#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.
#PF(fault-code) If a page fault occurs.
#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD If the LOCK prefix is used.
Real-Address Mode Exceptions
#GP If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS If a memory operand effective address is outside the SS segment limit.
#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.
#UD If the LOCK prefix is used.
Virtual-8086 Mode Exceptions
#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS(0) If a memory operand effective address is outside the SS segment limit.
#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.
#PF(fault-code) If a page fault occurs.
#AC(0) If alignment checking is enabled and an unaligned memory reference is made.
#UD If the LOCK prefix is used.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
#SS(0) If a memory address referencing the SS segment is in a non-canonical form.
#GP(0) If the memory address is in a non-canonical form.
#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.
#MF If there is a pending x87 FPU exception.
#PF(fault-code) If a page fault occurs.
#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD If the LOCK prefix is used.
FDIV/FDIVP/FIDIV—Divide Vol. 2A 3-335