rorx

Rotate Right Logical Without Affecting Flags

RORX r32, r/m32, imm8

Rotate right with immediate. No flags update.

Pseudocode Operation

count ← src2 & ((operand_size == 64) ? 0x3F : 0x1F); dest ← (src1 >> count) | (src1 << (operand_size - count));

Example

RORX eax, ebx, 3

Encoding

Binary Layout

VEX

opcode

ModRM

Format VEX

Opcode VEX.LZ.F2.0F3A.W0 F0 /r ib

Extension BMI2

Operands

dest
32-bit general-purpose register (e.g. EAX)
src1
32-bit register or memory
src2
8-bit signed immediate

Reference

View in Intel® 64 and IA-32 Architectures SDM ↗ Intel® SDM

Instruction Forms

Opcode	Instruction	Op/En	64/32-bit Mode	CPUID	Description
VEX.LZ.F2.0F3A.W0 F0 /r ib	RORX r32, r/m32, imm8	RMI	V/V	BMI2	Rotate 32-bit r/m32 right imm8 times and load into r32 without affecting arithmetic flags.
VEX.LZ.F2.0F3A.W1 F0 /r ib	RORX r64, r/m64, imm8	RMI	V/N.E.	BMI2	Rotate 64-bit r/m64 right imm8 times and load into r64 without affecting arithmetic flags.

Description

Rotates the bits of source operand right by the count value specified in imm8 without affecting arithmetic flags. The result is written to the destination operand. This instruction is not supported in real mode and virtual-8086 mode. The operand size is always 32 bits if not in 64-bit mode. In 64-bit mode operand size 64 requires VEX.W1. VEX.W1 is ignored in non-64-bit modes. An attempt to execute this instruction with VEX.L not equal to 0 will cause #UD.

Operation

IF (OperandSize = 32)
y := imm8 AND 1FH;
DEST := (SRC >> y) | (SRC << (32-y));
ELSEIF (OperandSize = 64)
y := imm8 AND 3FH;
DEST := (SRC >> y) | (SRC << (64-y));
FI;

Intel C/C++ Compiler Intrinsic Equivalent

Auto-generated from high-level language.

Flags Affected

None.

Exceptions

SIMD Floating-Point Exceptions