fild

Load Integer

FILD m16int/m32int/m64int

Converts integer in memory to double-extended-precision float and pushes to ST(0).

Details

Loads a signed integer (16-bit, 32-bit, or 64-bit) from memory, converts it to 80-bit extended precision floating-point, and pushes onto the x87 register stack (ST(0)). Stack pointer is decremented; conversion is exact and raises no precision or rounding exceptions unless stack overflow occurs. No CPU flags are modified.

Pseudocode Operation

ST(0) ← convert_integer_to_fp80(memory)
TOP ← TOP - 1
if TOP underflow: raise x87_stack_fault

Example

FILD m16int/m32int/m64int

Encoding

Binary Layout
DF
+0
ModRM
+1
 
Format Legacy
Opcode DF /0
Extension x87 FPU

Operands

  • src
    Integer Memory

Reference (Intel® SDM)

Instruction Forms

Opcode Instruction Op/En 64/32-bit Mode CPUID Description
DF /0 FILD m16int Valid Valid Push m16int onto the FPU register stack.
DB /0 FILD m32int Valid Valid Push m32int onto the FPU register stack.
DF /5 FILD m64int Valid Valid Push m64int onto the FPU register stack.

Description

Converts the signed-integer source operand into double extended-precision floating-point format and pushes the value onto the FPU register stack. The source operand can be a word, doubleword, or quadword integer. It is loaded without rounding errors. The sign of the source operand is preserved. This instruction’s operation is the same in non-64-bit modes and 64-bit mode.

Operation

TOP := TOP − 1;
ST(0) := ConvertToDoubleExtendedPrecisionFP(SRC);

Exceptions

Protected Mode Exceptions

#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register contains a NULL segment selector. #SS(0) If a memory operand effective address is outside the SS segment limit. #NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. #PF(fault-code) If a page fault occurs. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. #UD If the LOCK prefix is used.

Real-Address Mode Exceptions

#GP If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. #SS If a memory operand effective address is outside the SS segment limit. #NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. #UD If the LOCK prefix is used.

Virtual-8086 Mode Exceptions

#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. #SS(0) If a memory operand effective address is outside the SS segment limit. #NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. #PF(fault-code) If a page fault occurs. #AC(0) If alignment checking is enabled and an unaligned memory reference is made. #UD If the LOCK prefix is used. FILD—Load Integer Vol. 2A 3-342

Compatibility Mode Exceptions

Same exceptions as in protected mode.

64-Bit Mode Exceptions

#SS(0) If a memory address referencing the SS segment is in a non-canonical form. #GP(0) If the memory address is in a non-canonical form. #NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. #MF If there is a pending x87 FPU exception. #PF(fault-code) If a page fault occurs. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. #UD If the LOCK prefix is used. FILD—Load Integer Vol. 2A 3-343