movntq

Move Non-Temporal Quadword

MOVNTQ m64, mm

Stores 64-bit MMX data bypassing cache.

Details

Stores a 64-bit quadword from an MMX register directly to memory, bypassing the L1 and L2 caches (non-temporal hint). This instruction provides a memory-ordering serialization point and can improve performance for streaming writes that do not benefit from caching. No CPU flags are affected.

Pseudocode Operation

[m64] ← mm (non-temporal write)

Example

MOVNTQ [rbp-8], mm

Encoding

Binary Layout
0F
+0
E7
+1
 
Format SSE
Opcode NP 0F E7 /r
Extension SSE

Operands

  • dest
    64-bit memory operand (quadword)
  • src
    64-bit MMX register

Reference (Intel® SDM)

Instruction Forms

Opcode Instruction Op/En 64/32-bit Mode CPUID Description
NP 0F E7 /r MOVNTQ m64, mm MR Valid Valid Move quadword from mm to m64 using nontemporal hint.

Description

Moves the quadword in the source operand (second operand) to the destination operand (first operand) using a non-temporal hint to minimize cache pollution during the write to memory. The source operand is an MMX technology register, which is assumed to contain packed integer data (packed bytes, words, or doublewords). The destination operand is a 64-bit memory location. The non-temporal hint is implemented by using a write combining (WC) memory type protocol when writing the data to memory. Using this protocol, the processor does not write the data into the cache hierarchy, nor does it fetch the corresponding cache line from memory into the cache hierarchy. The memory type of the region being written to can override the non-temporal hint, if the memory address specified for the non-temporal store is in an uncacheable (UC) or write protected (WP) memory region. For more information on non-temporal stores, see “Caching of Temporal vs. Non-Temporal Data” in Chapter 10 in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1. Because the WC protocol uses a weakly-ordered memory consistency model, a fencing operation implemented with the SFENCE or MFENCE instruction should be used in conjunction with MOVNTQ instructions if multiple processors might use different memory types to read/write the destination memory locations. This instruction’s operation is the same in non-64-bit modes and 64-bit mode.

Operation

DEST := SRC;

Intel C/C++ Compiler Intrinsic Equivalent

MOVNTQ void _mm_stream_pi(__m64 * p, __m64 a)

Exceptions

SIMD Floating-Point Exceptions

None.

Other Exceptions

See Section 25.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B. MOVNTQ—Store of Quadword Using Non-Temporal Hint Vol. 2B 4-99