sahf

Store AH into Flags

SAHF

Loads SF, ZF, AF, PF, and CF from AH.

Details

Loads the lower byte of EFLAGS from the AH register, restoring flags CF, PF, AF, ZF, and SF. The upper bits of EFLAGS (IF, TF, DF, OF, NT, RF, VM, AC, VIF, VIP, ID) are unaffected. This is commonly used to restore previously saved flag state.

Pseudocode Operation

CF ← AH[0]; PF ← AH[2]; AF ← AH[4]; ZF ← AH[6]; SF ← AH[7];

Example

SAHF

Encoding

Binary Layout
9E
+0
 
Format Legacy
Opcode 9E
Extension Base

Operands

Reference (Intel® SDM)

Instruction Forms

Opcode Instruction Op/En 64/32-bit Mode CPUID Description
9E SAHF ZO Valid Invalid* Loads SF, ZF, AF, PF, and CF from AH into the EFLAGS register.

Description

Loads the SF, ZF, AF, PF, and CF flags of the EFLAGS register with values from the corresponding bits in the AH register (bits 7, 6, 4, 2, and 0, respectively). Bits 1, 3, and 5 of register AH are ignored; the corresponding reserved bits (1, 3, and 5) in the EFLAGS register remain as shown in the “Operation” section below. This instruction executes as described above in compatibility mode and legacy mode. It is valid in 64-bit mode only if CPUID.80000001H:ECX.LAHF_SAHF_64[0] = 1.

Operation

IF IA-64 Mode
THEN
IF CPUID.80000001H:ECX[0] = 1;
THEN
RFLAGS(SF:ZF:0:AF:0:PF:1:CF) := AH;
ELSE
#UD;
FI
ELSE
EFLAGS(SF:ZF:0:AF:0:PF:1:CF) := AH;
FI;

Flags Affected

The SF, ZF, AF, PF, and CF flags are loaded with values from the AH register. Bits 1, 3, and 5 of the EFLAGS register are unaffected, with the values remaining 1, 0, and 0, respectively.

Exceptions

Protected Mode Exceptions

None.

Real-Address Mode Exceptions

None.

Virtual-8086 Mode Exceptions

None.

Compatibility Mode Exceptions

None. SAHF—Store AH Into Flags Vol. 2B 4-601

64-Bit Mode Exceptions

#UD If CPUID.80000001H:ECX.LAHF_SAHF_64[0] = 0. If the LOCK prefix is used. SAHF—Store AH Into Flags Vol. 2B 4-602