cmpxchg

Compare and Exchange

CMPXCHG r/m, r

Compares accumulator with dest; if equal, dest = src; else accumulator = dest.

Details

Compares an implicit accumulator (AL/AX/EAX/RAX) with dest; if equal, src is written to dest and ZF is set; otherwise dest is written to the accumulator and ZF is cleared. Sets OF, SF, ZF, AF, CF, PF based on the comparison. Available in 386+ with size variants 8/16/32/64-bit; used for atomic compare-and-swap operations in lock-free code.

Pseudocode Operation

if (size == 8) {
  if (AL == dest) { dest ← src; ZF ← 1; } else { AL ← dest; ZF ← 0; }
} else if (size == 16) {
  if (AX == dest) { dest ← src; ZF ← 1; } else { AX ← dest; ZF ← 0; }
} else if (size == 32) {
  if (EAX == dest) { dest ← src; ZF ← 1; } else { EAX ← dest; ZF ← 0; }
} else { /* size == 64 */
  if (RAX == dest) { dest ← src; ZF ← 1; } else { RAX ← dest; ZF ← 0; }
}
OF, SF, AF, CF, PF ← undefined (or set by comparison result)

Example

CMPXCHG rbx, rax

Encoding

Binary Layout

Format Legacy

Opcode 0F B1

Extension Base

Operands

dest
Register or memory operand
src
General-purpose register

Reference (Intel® SDM)

Instruction Forms

Opcode	Instruction	Op/En	64/32-bit Mode	Description
0F B0/r	CMPXCHG r/m8, r8	MR	Valid Valid2	Compare AL with r/m8. If equal, ZF is set and r8 is loaded into r/m8. Else, clear ZF and load r/m8 into AL.
0F B1/r	CMPXCHG r/m16, r16	MR	Valid Valid2	Compare AX with r/m16. If equal, ZF is set and r16 is loaded into r/m16. Else, clear ZF and load r/m16 into AX.
0F B1/r	CMPXCHG r/m32, r32	MR	Valid Valid2	Compare EAX with r/m32. If equal, ZF is set and r32 is loaded into r/m32. Else, clear ZF and load r/m32 into EAX.
REX.W + 0F B1/r	CMPXCHG r/m64, r64	MR	Valid N.E.	Compare RAX with r/m64. If equal, ZF is set and r64 is loaded into r/m64. Else, clear ZF and load r/m64 into RAX.

Description

Compares the value in the AL, AX, EAX, or RAX register with the first operand (destination operand). If the two values are equal, the second operand (source operand) is loaded into the destination operand. Otherwise, the destination operand is loaded into the AL, AX, EAX or RAX register. RAX register is available only in 64-bit mode. This instruction can be used with a LOCK prefix to allow the instruction to be executed atomically. To simplify the interface to the processor’s bus, the destination operand receives a write cycle without regard to the result of the comparison. The destination operand is written back if the comparison fails; otherwise, the source operand is written into the destination. (The processor never produces a locked read without also producing a locked write.) In 64-bit mode, the instruction’s default operation size is 32 bits. Use of the REX.R prefix permits access to additional registers (R8-R15). Use of the REX.W prefix promotes operation to 64 bits. See the summary chart at the beginning of this section for encoding data and limits. IA-32 Architecture Compatibility This instruction is not supported on Intel processors earlier than the Intel486 processors.

Operation

(* Accumulator = AL, AX, EAX, or RAX depending on whether a byte, word, doubleword, or quadword comparison is being performed *)
TEMP := DEST
IF accumulator = TEMP
THEN
ZF := 1;
DEST := SRC;
ELSE
ZF := 0;
accumulator := TEMP;
DEST := TEMP;
FI;


CMPXCHG—Compare and Exchange                                                                                                              Vol. 2A 3-194

Flags Affected

The ZF flag is set if the values in the destination operand and register AL, AX, or EAX are equal; otherwise it is cleared. The CF, PF, AF, SF, and OF flags are set according to the results of the comparison operation.

Exceptions

Protected Mode Exceptions

#GP(0) If the destination is located in a non-writable segment. If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register contains a NULL segment selector. #SS(0) If a memory operand effective address is outside the SS segment limit. #PF(fault-code) If a page fault occurs. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. #UD If the LOCK prefix is used but the destination is not a memory operand.

Real-Address Mode Exceptions

#GP If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. #SS If a memory operand effective address is outside the SS segment limit. #UD If the LOCK prefix is used but the destination is not a memory operand.

Virtual-8086 Mode Exceptions

#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. #SS(0) If a memory operand effective address is outside the SS segment limit. #PF(fault-code) If a page fault occurs. #AC(0) If alignment checking is enabled and an unaligned memory reference is made. #UD If the LOCK prefix is used but the destination is not a memory operand.

Compatibility Mode Exceptions

Same exceptions as in protected mode.

64-Bit Mode Exceptions

#SS(0) If a memory address referencing the SS segment is in a non-canonical form. #GP(0) If the memory address is in a non-canonical form. #PF(fault-code) If a page fault occurs. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. #UD If the LOCK prefix is used but the destination is not a memory operand. CMPXCHG—Compare and Exchange Vol. 2A 3-195