vpshad
Vector Packed Shift Arithmetic Doubleword
Shifts doublewords arithmetically.
Pseudocode Operation
for i = 0 to 3 {
if (imm8 >= 0) {
xmm1[32*i:32*i+31] ← (xmm2/m128[32*i:32*i+31]) << imm8
} else {
xmm1[32*i:32*i+31] ← (xmm2/m128[32*i:32*i+31]) >> (-imm8) // arithmetic shift
}
}Example
Encoding
Operands
-
dest
128-bit XMM SIMD register -
src1
128-bit XMM SIMD register or Memory operand -
src2
8-bit signed immediate
Related
More in XOP
Reference
Instruction Forms
| Opcode | Instruction | Op/En | 64/32-bit Mode | CPUID | Description |
|---|---|---|---|---|---|
| 8F RXB.09 0.count.0.00 9A /r | VPSHAD xmm1, xmm2/mem128, xmm3 | ||||
| 8F RXB.09 1.src.0.00 9A /r | VPSHAD xmm1, xmm2, xmm3/mem128 |
Description
Doublewords Shifts each signed doubleword of the source operand as specified by a count byte and writes the result to the corresponding doubleword of the destination. The count bytes are 8-bit signed two's-complement values located in the low-order byte of the corresponding doubleword of the count operand. When the count value is positive, bits are shifted to the left (toward the more significant bit positions). Zeros are shifted in at the right end (least-significant bit) of the doubleword. When the count value is negative, bits are shifted to the right (toward the least significant bit positions). The most significant bit (sign bit) is replicated and shifted in at the left end (most-significant bit) of the doubleword. There are three operands: VPSHAD dest, src, count The destination (dest) is an XMM register specified by ModRM.reg. Both src and count are configured by XOP.W. • When XOP.W = 0, count is an XMM register specified by XOP.vvvv and src is either an XMM register or a memory location specified by ModRM.r/m. • When XOP.W = 1, count is either an XMM register or a memory location specified by ModRM.r/m and src is an XMM register specified by XOP.vvvv. Bits [255:128] of the YMM register that corresponds to the destination are cleared.