vpshad

Vector Packed Shift Arithmetic Doubleword

VPSHAD xmm1, xmm2/m128, imm8

Shifts doublewords arithmetically.

Details

The Vector Packed Shift Arithmetic Doubleword instruction shifts doublewords arithmetically.

Pseudocode Operation

// Shifts doublewords arithmetically

Example

VPSHAD xmm1, xmm2/m128, 3

Encoding

Binary Layout
VEX
+0
opcode
+3
ModRM
+4
 
Format XOP
Opcode 8F ... 9A
Extension XOP

Operands

  • dest
    128-bit XMM SIMD register
  • src1
    128-bit XMM SIMD register or Memory operand
  • src2
    8-bit signed immediate