blsfill
Bit Line Set Fill
Sets all bits below lowest set bit ((x-1) | x).
Pseudocode Operation
result ← (src - 1) | src; dest ← result; ZF ← (result == 0); SF ← result[31]; CF ← undefined; OF ← undefined; PF ← undefined;Example
Encoding
Operands
-
dest
32-bit general-purpose register (e.g. EAX) -
src
32-bit register or memory
Related
More in TBM
Reference
Instruction Forms
| Opcode | Instruction | Op/En | 64/32-bit Mode | CPUID | Description |
|---|---|---|---|---|---|
| 8F RXB.09 0.dest.0.00 01 /2 | BLSFILL reg32, reg/mem32 | ||||
| 8F RXB.09 1.dest.0.00 01 /2 | BLSFILL reg64, reg/mem64 |
Description
Finds the least significant one bit in the source operand, sets all bits below that bit to 1 and writes the result to the destination. If there is no one bit in the source operand, the destination is written with all ones. This instruction has two operands: BLSFILL dest, src In 64-bit mode, the operand size is determined by the value of XOP.W. If XOP.W is 1, the operand size is 64-bit; if XOP.W is 0, the operand size is 32-bit. In 32-bit mode, XOP.W is ignored. 16-bit operands are not supported. The destination (dest) is a general purpose register. The source operand (src) is a general purpose register or a memory operand. The BLSFILL instruction effectively performs a bit-wise logical or of the source operand and the result of subtracting 1 from the source operand, and stores the result to the destination register: sub tmp, src, 1 or dest, tmp, src The value of the carry flag of rFLAGs is generated by the sub pseudo-instruction and the remaining arithmetic flags are generated by the or pseudo-instruction. The BLSFILL instruction is a TBM instruction. Support for this instruction is indicated by CPUID Fn8000_0001_ECX[TBM] = 1. For more information on using the CPUID instruction, see the instruction reference page for the CPUID instruction on page 165. For a description of all feature flags related to instruction subset support, see Appendix D, “Instruction Subsets and CPUID Feature Flags,” on page 593.