vshuff32x4

Shuffle Packed Float32x4

VSHUFF32X4 zmm1 {k1}, zmm2, zmm3/m512, imm8

Shuffles 128-bit blocks of single-precision floats.

Details

Shuffles 128-bit blocks (each containing four 32-bit floats) from two ZMM sources according to an 8-bit immediate control, writing the result to the destination ZMM register. No flags are modified. Requires AVX-512F; the immediate selects which 128-bit quadwords are interleaved from the two sources. Opmask k1 controls which result elements are written.

Pseudocode Operation

temp ← 0
for i in 0 to 3:
  sel1 ← (imm8 >> (i*2)) & 0x3
  sel2 ← (imm8 >> (4 + i*2)) & 0x3
  temp[i*128 : (i+1)*128] ← ZMM2[sel1*128 : (sel1+1)*128]
  temp[(i+4)*128 : (i+5)*128] ← ZMM3/M512[sel2*128 : (sel2+1)*128]
for i in 0 to 15:
  if k1[i] == 1:
    ZMM1[i*32 : (i+1)*32] ← temp[i*32 : (i+1)*32]
  else if zeroing == true:
    ZMM1[i*32 : (i+1)*32] ← 0

Example

VSHUFF32X4 zmm1, zmm2, zmm3/m512, 3

Encoding

Binary Layout

EVEX

Format EVEX

Opcode EVEX.256.66.0F3A.W0 23 /r ib

Extension AVX-512F

Operands

dest
512-bit ZMM AVX-512 register
src1
512-bit ZMM AVX-512 register
src2
512-bit ZMM AVX-512 register or Memory operand
src3
8-bit signed immediate

Reference (Intel® SDM)

Instruction Forms

Opcode	Instruction	Op/En	64/32-bit Mode	CPUID	Description
EVEX.256.66.0F3A.W0 23 /r ib	VSHUFF32X4 ymm1{k1}{z}, ymm2, ymm3/m256/m32bcst, imm8	A	V/V	(AVX512VL AND AVX512F) OR AVX10.1	Shuffle 128-bit packed single-precision floatingpoint values selected by imm8 from ymm2 and ymm3/m256/m32bcst and place results in ymm1 subject to writemask k1.
EVEX.256.66.0F3A.W1 23 /r ib	VSHUFF64X2 ymm1{k1}{z}, ymm2, ymm3/m256/m64bcst, imm8	A	V/V	(AVX512VL AND AVX512F) OR AVX10.1	Shuffle 128-bit packed double precision floatingpoint values selected by imm8 from ymm2 and ymm3/m256/m64bcst and place results in ymm1 subject to writemask k1.
EVEX.256.66.0F3A.W0 43 /r ib	VSHUFI32X4 ymm1{k1}{z}, ymm2, ymm3/m256/m32bcst, imm8	A	V/V	(AVX512VL AND AVX512F) OR AVX10.1	Shuffle 128-bit packed double-word values selected by imm8 from ymm2 and ymm3/m256/m32bcst and place results in ymm1 subject to writemask k1.
EVEX.256.66.0F3A.W1 43 /r ib	VSHUFI64X2 ymm1{k1}{z}, ymm2, ymm3/m256/m64bcst, imm8	A	V/V	(AVX512VL AND AVX512F) OR AVX10.1	Shuffle 128-bit packed quad-word values selected by imm8 from ymm2 and ymm3/m256/m64bcst and place results in ymm1 subject to writemask k1.

Instruction Operand Encoding

Op/En	Tuple Type	Operand 1	Operand 2	Operand 3	Operand 4
A	Full	ModRM:reg (w)	EVEX.vvvv (r)	ModRM:r/m (r)	N/A

Description

256-bit Version: Moves one of the two 128-bit packed single precision floating-point values from the first source operand (second operand) into the low 128-bit of the destination operand (first operand); moves one of the two packed 128-bit floating-point values from the second source operand (third operand) into the high 128-bit of the destination operand. The selector operand (third operand) determines which values are moved to the destination operand. 512-bit Version: Moves two of the four 128-bit packed single precision floating-point values from the first source operand (second operand) into the low 256-bit of each double qword of the destination operand (first operand); moves two of the four packed 128-bit floating-point values from the second source operand (third operand) into the high 256-bit of the destination operand. The selector operand (third operand) determines which values are moved to the destination operand. VSHUFF32x4/VSHUFF64x2/VSHUFI32x4/VSHUFI64x2—Shuffle Packed Values at 128-Bit Granularity Vol. 2C 5-750 The first source operand is a vector register. The second source operand can be a ZMM register, a 512-bit memory location or a 512-bit vector broadcasted from a 32/64-bit memory location. The destination operand is a vector register. The writemask updates the destination operand with the granularity of 32/64-bit data elements.

Operation

Select2(SRC, control) {
CASE (control[0]) OF
0:  TMP := SRC[127:0];
1:  TMP := SRC[255:128];
ESAC;
RETURN TMP
}

Select4(SRC, control) {
CASE (control[1:0]) OF
0:  TMP := SRC[127:0];
1:  TMP := SRC[255:128];
2:  TMP := SRC[383:256];
3:  TMP := SRC[511:384];
ESAC;
RETURN TMP
}

VSHUFF32x4 (EVEX versions)
(KL, VL) = (8, 256), (16, 512)
FOR j := 0 TO KL-1
i := j * 32
IF (EVEX.b = 1) AND (SRC2 *is memory*)
THEN TMP_SRC2[i+31:i] := SRC2[31:0]
ELSE TMP_SRC2[i+31:i] := SRC2[i+31:i]
FI;
ENDFOR;
IF VL = 256
TMP_DEST[127:0] := Select2(SRC1[255:0], imm8[0]);
TMP_DEST[255:128] := Select2(SRC2[255:0], imm8[1]);
FI;
IF VL = 512
TMP_DEST[127:0] := Select4(SRC1[511:0], imm8[1:0]);
TMP_DEST[255:128] := Select4(SRC1[511:0], imm8[3:2]);
TMP_DEST[383:256] := Select4(TMP_SRC2[511:0], imm8[5:4]);
TMP_DEST[511:384] := Select4(TMP_SRC2[511:0], imm8[7:6]);
FI;
FOR j := 0 TO KL-1
i := j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+31:i] := TMP_DEST[i+31:i]
ELSE
IF *merging-masking*                                 ; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE *zeroing-masking*                            ; zeroing-masking
THEN DEST[i+31:i] := 0
FI;
FI;


VSHUFF32x4/VSHUFF64x2/VSHUFI32x4/VSHUFI64x2—Shuffle Packed Values at 128-Bit Granularity                                      Vol. 2C 5-751
ENDFOR
DEST[MAXVL-1:VL] := 0

VSHUFF64x2 (EVEX 512-bit version)
(KL, VL) = (4, 256), (8, 512)
FOR j := 0 TO KL-1
i := j * 64
IF (EVEX.b = 1) AND (SRC2 *is memory*)
THEN TMP_SRC2[i+63:i] := SRC2[63:0]
ELSE TMP_SRC2[i+63:i] := SRC2[i+63:i]
FI;
ENDFOR;
IF VL = 256
TMP_DEST[127:0] := Select2(SRC1[255:0], imm8[0]);
TMP_DEST[255:128] := Select2(SRC2[255:0], imm8[1]);
FI;
IF VL = 512
TMP_DEST[127:0] := Select4(SRC1[511:0], imm8[1:0]);
TMP_DEST[255:128] := Select4(SRC1[511:0], imm8[3:2]);
TMP_DEST[383:256] := Select4(TMP_SRC2[511:0], imm8[5:4]);
TMP_DEST[511:384] := Select4(TMP_SRC2[511:0], imm8[7:6]);
FI;
FOR j := 0 TO KL-1
i := j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+63:i] := TMP_DEST[i+63:i]
ELSE
IF *merging-masking*                                 ; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE *zeroing-masking*                            ; zeroing-masking
THEN DEST[i+63:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0

VSHUFI32x4 (EVEX 512-bit version)
(KL, VL) = (8, 256), (16, 512)
FOR j := 0 TO KL-1
i := j * 32
IF (EVEX.b = 1) AND (SRC2 *is memory*)
THEN TMP_SRC2[i+31:i] := SRC2[31:0]
ELSE TMP_SRC2[i+31:i] := SRC2[i+31:i]
FI;
ENDFOR;
IF VL = 256
TMP_DEST[127:0] := Select2(SRC1[255:0], imm8[0]);
TMP_DEST[255:128] := Select2(SRC2[255:0], imm8[1]);
FI;
IF VL = 512
TMP_DEST[127:0] := Select4(SRC1[511:0], imm8[1:0]);
TMP_DEST[255:128] := Select4(SRC1[511:0], imm8[3:2]);
TMP_DEST[383:256] := Select4(TMP_SRC2[511:0], imm8[5:4]);
TMP_DEST[511:384] := Select4(TMP_SRC2[511:0], imm8[7:6]);


VSHUFF32x4/VSHUFF64x2/VSHUFI32x4/VSHUFI64x2—Shuffle Packed Values at 128-Bit Granularity                                      Vol. 2C 5-752
FI;
FOR j := 0 TO KL-1
i := j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+31:i] := TMP_DEST[i+31:i]
ELSE
IF *merging-masking*                                 ; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE *zeroing-masking*                            ; zeroing-masking
THEN DEST[i+31:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0

VSHUFI64x2 (EVEX 512-bit version)
(KL, VL) = (4, 256), (8, 512)
FOR j := 0 TO KL-1
i := j * 64
IF (EVEX.b = 1) AND (SRC2 *is memory*)
THEN TMP_SRC2[i+63:i] := SRC2[63:0]
ELSE TMP_SRC2[i+63:i] := SRC2[i+63:i]
FI;
ENDFOR;
IF VL = 256
TMP_DEST[127:0] := Select2(SRC1[255:0], imm8[0]);
TMP_DEST[255:128] := Select2(SRC2[255:0], imm8[1]);
FI;
IF VL = 512
TMP_DEST[127:0] := Select4(SRC1[511:0], imm8[1:0]);
TMP_DEST[255:128] := Select4(SRC1[511:0], imm8[3:2]);
TMP_DEST[383:256] := Select4(TMP_SRC2[511:0], imm8[5:4]);
TMP_DEST[511:384] := Select4(TMP_SRC2[511:0], imm8[7:6]);
FI;
FOR j := 0 TO KL-1
i := j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+63:i] := TMP_DEST[i+63:i]
ELSE
IF *merging-masking*                                 ; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE *zeroing-masking*                            ; zeroing-masking
THEN DEST[i+63:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0





VSHUFF32x4/VSHUFF64x2/VSHUFI32x4/VSHUFI64x2—Shuffle Packed Values at 128-Bit Granularity                                      Vol. 2C 5-753

Intel C/C++ Compiler Intrinsic Equivalent

VSHUFI32x4 __m512i _mm512_shuffle_i32x4(__m512i a, __m512i b, int imm);
VSHUFI32x4 __m512i _mm512_mask_shuffle_i32x4(__m512i s, __mmask16 k, __m512i a, __m512i b, int imm);
VSHUFI32x4 __m512i _mm512_maskz_shuffle_i32x4( __mmask16 k, __m512i a, __m512i b, int imm);
VSHUFI32x4 __m256i _mm256_shuffle_i32x4(__m256i a, __m256i b, int imm);
VSHUFI32x4 __m256i _mm256_mask_shuffle_i32x4(__m256i s, __mmask8 k, __m256i a, __m256i b, int imm);
VSHUFI32x4 __m256i _mm256_maskz_shuffle_i32x4( __mmask8 k, __m256i a, __m256i b, int imm);
VSHUFF32x4 __m512 _mm512_shuffle_f32x4(__m512 a, __m512 b, int imm);
VSHUFF32x4 __m512 _mm512_mask_shuffle_f32x4(__m512 s, __mmask16 k, __m512 a, __m512 b, int imm);
VSHUFF32x4 __m512 _mm512_maskz_shuffle_f32x4( __mmask16 k, __m512 a, __m512 b, int imm);
VSHUFI64x2 __m512i _mm512_shuffle_i64x2(__m512i a, __m512i b, int imm);
VSHUFI64x2 __m512i _mm512_mask_shuffle_i64x2(__m512i s, __mmask8 k, __m512i b, __m512i b, int imm);
VSHUFI64x2 __m512i _mm512_maskz_shuffle_i64x2( __mmask8 k, __m512i a, __m512i b, int imm);
VSHUFF64x2 __m512d _mm512_shuffle_f64x2(__m512d a, __m512d b, int imm);
VSHUFF64x2 __m512d _mm512_mask_shuffle_f64x2(__m512d s, __mmask8 k, __m512d a, __m512d b, int imm);
VSHUFF64x2 __m512d _mm512_maskz_shuffle_f64x2( __mmask8 k, __m512d a, __m512d b, int imm);

Exceptions

SIMD Floating-Point Exceptions

None.

Other Exceptions

See Table 2-52, “Type E4NF Class Exception Conditions.” Additionally: #UD If EVEX.L’L = 0 for VSHUFF32x4/VSHUFF64x2. VSHUFF32x4/VSHUFF64x2/VSHUFI32x4/VSHUFI64x2—Shuffle Packed Values at 128-Bit Granularity Vol. 2C 5-754