vrsqrt14ps
Compute Approximate Reciprocal Square Root (14-bit)
Approximate 1/sqrt(x) with 2^-14 error.
Pseudocode Operation
for i in 0 to 15:
if k1[i] == 1 or k1_merge_mode == 0:
dest.f32[i] ← approx_rsqrt14(src.f32[i])
else:
dest.f32[i] ← 0Example
Encoding
Operands
-
dest
512-bit ZMM AVX-512 register -
src
512-bit ZMM AVX-512 register or Memory operand
Related
More in AVX-512F
Reference
Instruction Forms
| Opcode | Instruction | Op/En | 64/32-bit Mode | CPUID | Description |
|---|---|---|---|---|---|
| EVEX.128.66.0F38.W0 4E /r | VRSQRT14PS xmm1 {k1}{z}, xmm2/m128/m32bcst | A | V/V | (AVX512VL AND AVX512F) OR AVX10.1 | Computes the approximate reciprocal square roots of the packed single-precision floating-point values in xmm2/m128/m32bcst and stores the results in xmm1. Under writemask. |
| EVEX.256.66.0F38.W0 4E /r | VRSQRT14PS ymm1 {k1}{z}, ymm2/m256/m32bcst | A | V/V | (AVX512VL AND AVX512F) OR AVX10.1 | Computes the approximate reciprocal square roots of the packed single-precision floating-point values in ymm2/m256/m32bcst and stores the results in ymm1. Under writemask. |
| EVEX.512.66.0F38.W0 4E /r | VRSQRT14PS zmm1 {k1}{z}, zmm2/m512/m32bcst | A | V/V | AVX512F OR AVX10.1 | Computes the approximate reciprocal square roots of the packed single-precision floating-point values in zmm2/m512/m32bcst and stores the results in zmm1. Under writemask. |
Instruction Operand Encoding
| Op/En | Tuple Type | Operand 1 | Operand 2 | Operand 3 | Operand 4 |
|---|---|---|---|---|---|
| A | Full | ModRM:reg (w) | ModRM:r/m (r) | N/A | N/A |
Description
This instruction performs a SIMD computation of the approximate reciprocals of the square roots of 16 packed single precision floating-point values in the source operand (the second operand) and stores the packed single precision floating-point results in the destination operand (the first operand) according to the writemask. The maximum relative error for this approximation is less than 2-14. EVEX.512 encoded version: The source operand can be a ZMM register, a 512-bit memory location or a 512-bit vector broadcasted from a 32-bit memory location. The destination operand is a ZMM register, conditionally updated using writemask k1. EVEX.256 encoded version: The source operand is a YMM register, a 256-bit memory location, or a 256-bit vector broadcasted from a 32-bit memory location. The destination operand is a YMM register, conditionally updated using writemask k1. EVEX.128 encoded version: The source operand is a XMM register, a 128-bit memory location, or a 128-bit vector broadcasted from a 32-bit memory location. The destination operand is a XMM register, conditionally updated using writemask k1. The VRSQRT14PS instruction is not affected by the rounding control bits in the MXCSR register. When a source value is a 0.0, an ∞ with the sign of the source value is returned. When the source operand is an +∞ then +ZERO value is returned. A denormal source value is treated as zero only if DAZ bit is set in MXCSR. Otherwise it is treated correctly and performs the approximation with the specified masked response. When a source value is a negative value (other than 0.0) a floating-point QNaN_indefinite is returned. When a source value is an SNaN or QNaN, the SNaN is converted to a QNaN or the source QNaN is returned. MXCSR exception flags are not affected by this instruction and floating-point exceptions are not reported. Note: EVEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD. A numerically exact implementation of VRSQRT14xx can be found at https://software.intel.com/en-us/articles/reference-implementations-for-IA-approximation-instructions-vrcp14-vrsqrt14-vrcp28-vrsqrt28-vexp2.
Operation
VRSQRT14PS (EVEX encoded versions) (KL, VL) = (4, 128), (8, 256), (16, 512) FOR j := 0 TO KL-1 i := j * 32 IF k1[j] OR *no writemask* THEN IF (EVEX.b = 1) AND (SRC *is memory*) THEN DEST[i+31:i] := APPROXIMATE(1.0/ SQRT(SRC[31:0])); ELSE DEST[i+31:i] := APPROXIMATE(1.0/ SQRT(SRC[i+31:i])); FI; ELSE IF *merging-masking* ; merging-masking THEN *DEST[i+31:i] remains unchanged* ELSE ; zeroing-masking DEST[i+31:i] := 0 FI; FI; ENDFOR; DEST[MAXVL-1:VL] := 0 Table 5-33. VRSQRT14PS Special Cases Input value Result value Comments Any denormal Normal Cannot generate overflow X = 2-2n 2n X < 0 QNaN_Indefinite Including -INF X = -0 -INF X = +0 +INF X = +INF +0
Intel C/C++ Compiler Intrinsic Equivalent
VRSQRT14PS __m512 _mm512_rsqrt14_ps( __m512 a); VRSQRT14PS __m512 _mm512_mask_rsqrt14_ps(__m512 s, __mmask16 k, __m512 a); VRSQRT14PS __m512 _mm512_maskz_rsqrt14_ps( __mmask16 k, __m512 a); VRSQRT14PS __m256 _mm256_rsqrt14_ps( __m256 a); VRSQRT14PS __m256 _mm256_mask_rsqrt14_ps(__m256 s, __mmask8 k, __m256 a); VRSQRT14PS __m256 _mm256_maskz_rsqrt14_ps( __mmask8 k, __m256 a); VRSQRT14PS __m128 _mm_rsqrt14_ps( __m128 a); VRSQRT14PS __m128 _mm_mask_rsqrt14_ps(__m128 s, __mmask8 k, __m128 a); VRSQRT14PS __m128 _mm_maskz_rsqrt14_ps( __mmask8 k, __m128 a);