stmxcsr

Store MXCSR Register

STMXCSR m32

Stores the MXCSR register to memory.

Details

Stores the 32-bit MXCSR control and status register to a 32-bit memory location. This instruction serializes execution and is typically used to save the SSE/SSE2/SSE3 floating-point state. No flags are modified by this instruction.

Pseudocode Operation

[dest] ← MXCSR;

Example

STMXCSR [rbp-4]

Encoding

Binary Layout
0F
+0
AE
+1
ModRM
+2
 
Format SSE
Opcode NP 0F AE /3
Extension SSE

Operands

  • dest
    32-bit memory operand

Reference (Intel® SDM)

Instruction Forms

Opcode Instruction Op/En 64/32-bit Mode CPUID Description
NP 0F AE /3 STMXCSR m32 M V/V SSE Store contents of MXCSR register to m32.
VEX.LZ.0F.WIG AE /3 VSTMXCSR m32 M V/V AVX Store contents of MXCSR register to m32.

Description

Stores the contents of the MXCSR control and status register to the destination operand. The destination operand is a 32-bit memory location. The reserved bits in the MXCSR register are stored as 0s. This instruction’s operation is the same in non-64-bit modes and 64-bit mode. VEX.L must be 0, otherwise instructions will #UD. Note: In VEX-encoded versions, VEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.

Operation

m32 := MXCSR;

Intel C/C++ Compiler Intrinsic Equivalent

_mm_getcsr(void)

Exceptions

SIMD Floating-Point Exceptions

None.

Other Exceptions

See Table 2-22, “Type 5 Class Exception Conditions,” additionally: #UD If VEX.L= 1, If VEX.vvvv ≠ 1111B. STMXCSR—Store MXCSR Register State Vol. 2B 4-675