vsqrtsh

Square Root Scalar Half-Precision

VSQRTSH xmm1 {k1}, xmm2/m16

Square root of low FP16 value.

Details

Computes the square root of the low-order half-precision (FP16) element and stores the scalar result in the low 16 bits of the destination, with upper 112 bits cleared or preserved based on write-mask. Uses EVEX encoding with optional masking and exception suppression. Rounding mode determined by MXCSR[15:13].

Pseudocode Operation

if (k1[0] || !masking_enabled) {
  dest[0:15] ← sqrt_FP16(src[0:15]);
} else {
  dest[0:15] ← preserve_or_zero(dest[0:15]);
}
dest[16:127] ← 0;

Example

VSQRTSH xmm1, xmm2/m16

Encoding

Binary Layout
EVEX
+0
51
+4
 
Format EVEX
Opcode EVEX.LLIG.F3.MAP5.W0 51 /r
Extension AVX-512-FP16

Operands

  • dest
    128-bit XMM SIMD register
  • src
    128-bit XMM SIMD register or Memory operand

Reference (Intel® SDM)

Instruction Forms

Opcode Instruction Op/En 64/32-bit Mode CPUID Description
EVEX.LLIG.F3.MAP5.W0 51 /r VSQRTSH xmm1{k1}{z}, xmm2, xmm3/m16 {er} A V/V AVX512_FP16 OR AVX10.1 Compute square root of the low FP16 value in xmm3/m16 and store the result in xmm1 subject to writemask k1. Bits 127:16 from xmm2 are copied to xmm1[127:16].

Instruction Operand Encoding

Op/En Tuple Type Operand 1 Operand 2 Operand 3 Operand 4
A Scalar ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) N/A

Description

This instruction performs a scalar FP16 square-root computation on the source operand and stores the FP16 result in the destination operand. Bits 127:16 of the destination operand are copied from the corresponding bits of the first source operand. Bits MAXVL-1:128 of the destination operand are zeroed. The low FP16 element of the destination is updated according to the writemask.

Operation

VSQRTSH dest{k1}, src1, src2
IF k1[0] or *no writemask*:
DEST.fp16[0] := SQRT(src2.fp16[0])
ELSE IF *zeroing*:
DEST.fp16[0] := 0
//else DEST.fp16[0] remains unchanged

DEST[127:16] := src1[127:16]
DEST[MAXVL-1:128] := 0

Intel C/C++ Compiler Intrinsic Equivalent

VSQRTSH __m128h _mm_mask_sqrt_round_sh (__m128h src, __mmask8 k, __m128h a, __m128h b, const int rounding);
VSQRTSH __m128h _mm_maskz_sqrt_round_sh (__mmask8 k, __m128h a, __m128h b, const int rounding);
VSQRTSH __m128h _mm_sqrt_round_sh (__m128h a, __m128h b, const int rounding);
VSQRTSH __m128h _mm_mask_sqrt_sh (__m128h src, __mmask8 k, __m128h a, __m128h b);
VSQRTSH __m128h _mm_maskz_sqrt_sh (__mmask8 k, __m128h a, __m128h b);
VSQRTSH __m128h _mm_sqrt_sh (__m128h a, __m128h b);

Exceptions

SIMD Floating-Point Exceptions

Invalid, Precision, Denormal

Other Exceptions

EVEX-encoded instructions, see Table 2-49, “Type E3 Class Exception Conditions.” VSQRTSH—Compute Square Root of Scalar FP16 Value Vol. 2C 5-767